[openib-general] [PATCH] mthca updates (2.6.8 dependent)

[Roland Dreier]

    Michael> I'm not sure you can rely on messages being ordered
    Michael> properly with regard to posted writes e.g. inside the
    Michael> chipset.

Hmm... that seems like a really ugly "feature" to allow interrupts to
pass posted writes within the chipset.

In any case in mthca I unconditionally rearm the EQ after polling it,
so I think my MSI-X implementation should work OK even if we have that
ordering problem.

 - R.