[openib-general] [PATCH] roland-uverbs: possible race condition

[Roland Dreier]

    Michael> Ordering matrix is documented within the PCIe base 1.0a
    Michael> specification.  The rules are fairly straight forward
    Michael> depending upon the capabilities being accessed.  Too much
    Michael> to type in here but to give you an idea:

    Michael> - INTx are treated as writes from a PCIe transaction
    Michael> perspective.

Thanks, I had found that matrix.  However I was not able to find any
language about ordering of interrupts and writes outside of the PCI
Express domain -- the question is whether an interrupt could pass a
memory write transaction upstream of the root complex.  For example,
one could imagine a PCIe host bridge for a CPU that has no provision
for in-band interrupt signaling, so the host bridge must signal all
interrupts by asserting an interrupt pin that is independent of the
CPU's memory bus.  In this case what guarantees ordering?  Another
similar situation would be a PCI-PCIe reverse bridge where the bridge
has to convert PCIe INTx messages to real PCI interrupt pins -- it
seems impossible for any ordering to be guaranteed.

In fact, section 6.1.3 of the PCIe spec says

    "Note that similarly to physical interrupt signals, the INTx
     emulation mechanism may potentially cause spurious interrupts that
     must be handled by the system software."

which is conspicuously silent on ordering issues but seems to me to be
saying "watch out."

Thanks,
  Roland