[openib-general] Re: openib and mellanox hca problem

[Michael Di Domenico]

On 2/8/06, Michael S. Tsirkin <mst at mellanox.co.il> wrote:
> Quoting Roland Dreier <rdreier at cisco.com>:
> > Certainly building with CONFIG_INFINIBAND_MTHCA_DEBUG=y would be a
> > good idea.  But even without debug, if we don't find a bridge, we
> > should see the warning from the code:
>
> Right, I wanded to check we got the right bus/device number, and it seems
> we did.

FYI...

Changed over to RHEL4 IA32 w/ SilverStorm Host Stack v3.2.0.0.21 and
now i get the below info and a working infiniband setup...

Since I have two servers, I'm going to leave this one working and try
openib on the second machine...

# uname -a
Linux linux14.silverstorm.com 2.6.9-5.ELsmp #1 SMP Wed Jan 5 19:30:39
EST 2005 i686 i686 i386 GNU/Linux

# lspci -vvv
06:03.0 PCI bridge: Mellanox Technologies MT23108 PCI Bridge (rev a1)
(prog-if 00 [Normal decode])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
ParErr- Stepping- SERR+ FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium
>TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size 10
        Bus: primary=06, secondary=07, subordinate=07, sec-latency=64
        I/O behind bridge: 0000f000-00000fff
        Memory behind bridge: fe500000-fe7fffff
        Prefetchable memory behind bridge: 00000000eac00000-00000000fbc00000
        Secondary status: 66Mhz+ FastB2B- ParErr- DEVSEL=medium
>TAbort- <TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
        Capabilities: [70] PCI-X bridge device.
                Secondary Status: 64bit+, 133MHz+, SCD-, USC-, SCO-, SRD- Freq=3
                Status: Bus=6 Dev=3 Func=0 64bit+ 133MHz+ SCD- USC-, SCO-, SRD-
                : Upstream: Capacity=512, Commitment Limit=512
                : Downstream: Capacity=128, Commitment Limit=128

07:00.0 InfiniBand: Mellanox Technologies MT23108 InfiniHost (rev a1)
        Subsystem: Mellanox Technologies MT23108 InfiniHost
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
ParErr- Stepping- SERR+ FastB2B-
        Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium
>TAbort- <TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size 10
        Interrupt: pin A routed to IRQ 217
        Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=1M]
        Region 2: Memory at fb000000 (64-bit, prefetchable) [size=8M]
        Region 4: Memory at f0000000 (64-bit, prefetchable) [size=128M]
        Capabilities: [40] MSI-X: Enable- Mask- TabSize=32
                Vector table: BAR=0 offset=00082000
                PBA: BAR=0 offset=00082200
        Capabilities: [50] Vital Product Data
        Capabilities: [60] Message Signalled Interrupts: 64bit+
Queue=0/5 Enable-
                Address: 0000000000000000  Data: 0000
        Capabilities: [70] PCI-X non-bridge device.
                Command: DPERE- ERO- RBC=3 OST=1
                Status: Bus=7 Dev=0 Func=0 64bit+ 133MHz+ SCD- USC-,
DC=simple, DMMRBC=3, DMOST=1, DMCRS=0, RSCEM-