[ofa-general] Re: [PATCH 2 of 3 for-2.6.24] mlx4: always fill MTTs from CPU

[Roland Dreier]

 > +	/* Reserved mtt entries must be aligned up to a cacheline boundary,
 > +	 * since the FW will write to them, while the driver writes to all
 > +	 * other mtt entries. (Note that the variable dev->caps.mtt_entry_sz
 > +	 * below is really the mtt segment size, not the raw entry size)
 > +	 */
 > +	num_mtt_res_bytes = ((dev->caps.reserved_mtts *
 > +			      (dev->caps.mtt_entry_sz / MLX4_MTT_ENTRY_PER_SEG)
 > +			     + L1_CACHE_BYTES - 1) /
 > +			     L1_CACHE_BYTES) * L1_CACHE_BYTES;

Shouldn't this be dma_get_cache_alignment() instead of L1_CACHE_BYTES
(which would match what mthca does)?

 - R.