[ofa-general][PATCH] mlx4: Completion EQ per cpu (MP support, Patch 10)
yevgenyp at mellanox.co.il
Wed Apr 23 03:41:15 PDT 2008
Shirley Ma wrote:
> Hello Yevgeny,
> Can you give more details of this patch? What's the relationship
> between CQ, EQ, port?
> I was thinking to implement it in upper layer. Is it better to
> implement in upper layer protocol, rather than device layer?
We refer EQs as interrupt vectors (each EQ is attched to Msi - X vector).
Creating multiple completion EQ's helps us to distribute the interrupt load
(and the software interrupt handling associated with it) among all CPUs.
For example, distributing TCP flows among multiple cores is important for
10GE devices to sustain wire-speed with lots of connections.
Each CQ is attached to an EQ and receives its completion interrupts from that EQ.
CQ and EQ are not per port.
Implementing this in in device layer allows all ULP's to use the feature.
We do not expose EQ allocation API, because there is no point creating more EQs
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