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<TITLE>RE: [openib-general] [PATCH] mthca updates (2.6.8 dependent)</TITLE>
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<P><FONT SIZE=2>> -----Original Message-----</FONT>
<BR><FONT SIZE=2>> From: Grant Grundler [<A HREF="mailto:iod00d@hp.com">mailto:iod00d@hp.com</A>] </FONT>
<BR><FONT SIZE=2>> Sent: Tuesday, August 31, 2004 7:00 AM</FONT>
<BR><FONT SIZE=2>> </FONT>
<BR><FONT SIZE=2>> On Mon, Aug 16, 2004 at 09:27:13PM +0300, Dror Goldenberg wrote:</FONT>
<BR><FONT SIZE=2>> > In PCI/PCIX, the interrupt is a wire, so it is not </FONT>
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<P><FONT SIZE=2>> </FONT>
<BR><FONT SIZE=2>> Dror,</FONT>
<BR><FONT SIZE=2>> I'm pretty sure you understand the issues but are using confusing</FONT>
<BR><FONT SIZE=2>> terminology:</FONT>
<BR><FONT SIZE=2>> o posted write. CPU does not wait for completion of write to </FONT>
<BR><FONT SIZE=2>> IO device o PIO write. Programmed IO - CPU write to IO </FONT>
<BR><FONT SIZE=2>> device. May or not be posted</FONT>
<BR><FONT SIZE=2>> and typically depends on chipset and which "space" (MMIO vs I/O</FONT>
<BR><FONT SIZE=2>> Port) is the target.</FONT>
<BR><FONT SIZE=2>> o PIO read. Programmed IO - CPU read stalls until completion </FONT>
<BR><FONT SIZE=2>> (may be MMIO</FONT>
<BR><FONT SIZE=2>> or I/O port space).</FONT>
<BR><FONT SIZE=2>> o DMA write: IO Device write to host memory (aka upstream)</FONT>
<BR><FONT SIZE=2>> o DMA read: Device command to retrieve data from host memory </FONT>
<BR><FONT SIZE=2>> (downstream) o DMA read return: completion portion of DMA </FONT>
<BR><FONT SIZE=2>> read command (upstream)</FONT>
<BR><FONT SIZE=2>> </FONT>
<BR><FONT SIZE=2>> A PIO Read "flushes" inflight DMA writes from a CPU </FONT>
<BR><FONT SIZE=2>> perspective because the CPU stalls until the PIO read completes.</FONT>
<BR><FONT SIZE=2>> </FONT>
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<P><FONT SIZE=2>Yes... it sounds much better. Thanks !</FONT>
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<P><FONT SIZE=2>> > In PCI-Express, the interrupt is a message, so it will work. The </FONT>
<BR><FONT SIZE=2>> > interrupt will just flush the data to the memory because it </FONT>
<BR><FONT SIZE=2>> maintain </FONT>
<BR><FONT SIZE=2>> > ordering with posted writes upstream.</FONT>
<BR><FONT SIZE=2>> </FONT>
<BR><FONT SIZE=2>> The MSI/MSI-X interrupt doesn't do anything.</FONT>
<BR><FONT SIZE=2>> The interrupt transaction is just another DMA Write and must </FONT>
<BR><FONT SIZE=2>> follow the PCI ordering rules like any other DMA write. The </FONT>
<BR><FONT SIZE=2>> destination address is just not a regular host memory location.</FONT>
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<P><FONT SIZE=2>I was talking about regular interrupts in PCI express. For PCI express</FONT>
<BR><FONT SIZE=2>MSI/MSI-X are plain DMA writes. However, good old interrupts in PCI</FONT>
<BR><FONT SIZE=2>express don't go on external wire. They just go on the same bus like </FONT>
<BR><FONT SIZE=2>the data, for that they use special PCI express messages. And, they</FONT>
<BR><FONT SIZE=2>maintain ordering like other any other DMA writes. So, although the</FONT>
<BR><FONT SIZE=2>same semantics of "old interrupts" is preserved, the behavior is a bit</FONT>
<BR><FONT SIZE=2>different in PCI express</FONT>
<BR><FONT SIZE=2> </FONT>
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