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It is the consensus within the industry that PIO Reads (MMIO) are pure
"evil" and should be avoided in any main line data path
including the interrupt path. They should be confined to
configuration / status / etc. checks and thus are very infrequent.
Designs that rely upon PIO Reads for anything in the performance path
tend to not succeed that well within the industry. This is
true across all processor architectures including x86 itself. The
problem only gets worse (not just because of the number of chip
crossings) but also because the amount of cycles stalled as clock speeds
increase. Some might contend that technology such as multi-thread
or predicted / delayed loads can mitigate this problem but I have yet to
see any real data to support such assertions. In general, designs
need to avoid using PIO Reads in the main data path period. I
believe most I/O and system architects from all companies will agree on
this point (I also know that many server IHV will also agree).<br><br>
Mike<br><br>
<br>
At 09:52 AM 1/24/2005, Grant Grundler wrote:<br>
<blockquote type=cite class=cite cite="">On Sun, Jan 23, 2005 at
11:06:34AM +0200, Michael S. Tsirkin wrote:<br>
> But, do they hurt perf on ia64 more than on x86?<br><br>
It does NOT depend on the CPU architecture.<br>
It depends on how many bridge chips are between the CPU and IO
device<br>
and which type of bus the MMIO read has to flow through.<br><br>
For ZX1 it's normally two (unless we add a PCI-PCI Bridge as well).<br>
Most x86 chipsets only have one unless they use the north/south<br>
bridge designs. IIRC, x86-64 with a single CPU also has one
bridge.<br><br>
For more discussion on HP ZX1 chips WRT MMIO reads, see:<br>
<x-tab> </x-tab>
<a href="http://iou.parisc-linux.org/ols2002/" eudora="autourl">
http://iou.parisc-linux.org/ols2002/</a><br><br>
hth,<br>
grant<br>
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