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<font size=3>At 11:24 PM 1/31/2005, Grant Grundler wrote:<br>
<blockquote type=cite class=cite cite="">On Mon, Jan 31, 2005 at
02:40:18PM -0800, Michael Krause wrote:<br>
> - INTx are treated as writes from a PCIe transaction
perspective.<br><br>
I remember the INTx are transactions once they hit the PCIe bus.<br>
But do PCIe native devices emit those INTx transactions
directly?<br><br>
For some reaon I was thinking INTx was still a physical IRQ line for<br>
legacy PCI compatibility.</font></blockquote><br>
All PCIe transactions are in-band TLP. Hence, an INTx is a special
write TLP but still a TLP even though they are a PCI compatibility
function.<br><br>
<br>
<blockquote type=cite class=cite cite=""><font size=3>...<br>
> - In general, all interrupts (line or MSI/MSI-X) should be strongly
ordered <br>
> relative to other write operations to avoid silent data corruption
from <br>
> occurring. As such, an interrupt should not pass a memory
write when being <br>
> processed by the chipset.<br><br>
Ok...I need to keep in mind your reply is for PCIe where
"interrupts" means "INTx
transaction".</font></blockquote><br>
Correct.<br><br>
<blockquote type=cite class=cite cite=""><font size=3>BTW, OS's using
legacy PCI OS drivers already do protect themselves from the DMA vs IRQ
line delivery races. Or at least linux does. MSI/MSI-X support was only
introduce a year or so ago - 4 or 5 years after MSI was introduced into
PCI 2.2 spec.</blockquote><br>
No one had really implemented a credible MSI. HP proposed MSI-X as
a natural extension of something we already developed 15+ years ago and
worked with others in the SIG to get it in place. I know of several
IHV who have now implemented and multiple OS are doing so as well.
Hopefully it will catch on and become the primary method for interrupt
delivery. It will also benefit new technology such as
virtualization where a MSI-X vector can now target a specific guest as
opposed to just a data value that has to be handled by a hypervisor.
<br><br>
Mike</font></body>
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