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<font size=3>At 12:53 PM 8/25/2006, Talpey, Thomas wrote:<br>
<blockquote type=cite class=cite cite="">At 03:23 PM 8/25/2006, Greg
Lindahl wrote:<br>
>On Fri, Aug 25, 2006 at 03:21:20PM -0400, mlakshmanan@silverstorm.com
wrote:<br>
><br>
>> I presume you meant invalidate the cache, not flush it, before
<br>
>accessing DMA'ed <br>
>> data. <br>
><br>
>Yes, this is what I meant. Sorry!<br><br>
Flush (sync for_device) before posting.<br>
Invalidate (sync for_cpu) before processing.<br><br>
On some architectures, these operations flush and/or invalidate<br>
i/o pipeline caches as well. As they should.</font></blockquote><br>
Many platforms have coherent I/O components so the explicit requirements
on software to participate are often eliminated.<br><br>
Mike</body>
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