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<p class="MsoNormal"><span style="color:#1D1D1D;background:white">==========================================================================</span><span style="color:#1D1D1D"><br>
<span style="background:white"> CALL FOR PAPERS</span><br>
<span style="background:white">==========================================================================</span><br>
<br>
<span style="background:white">3rd IEEE International Workshop on RESource DISaggregation in High</span><br>
<span style="background:white">Performance Computing (RESDIS?23)</span><br>
<br>
<span style="background:white">To be held in conjunction with The International Conference for High</span><br>
<span style="background:white">Performance Computing, Networking, Storage and Analysis (SC?23) on November 17,</span><br>
<span style="background:white">2023</span><br>
<br>
<span style="background:white">==========================================================================</span><br>
<span style="background:white"> <span class="apple-converted-space"> <a href="https://resdis.github.io/">https://resdis.github.io/</a></span></span><br>
<span style="background:white">==========================================================================</span><br>
<br>
<span style="background:white">Disaggregation is an emerging compute paradigm that splits existing monolithic</span><br>
<span style="background:white">servers into a number of consolidated single-resource pools that communicate</span><br>
<span style="background:white">over a fast interconnect. This model decouples individual hardware resources,</span><br>
<span style="background:white">including tightly coupled ones such as processors and memory, and enables the</span><br>
<span style="background:white">composition of logical compute platforms with flexible and dynamic hardware</span><br>
<span style="background:white">configurations.</span><br>
<br>
<span style="background:white">The concept of disaggregation is driven by various recent trends in</span><br>
<span style="background:white">computation. From an application perspective, the increasing importance of</span><br>
<span style="background:white">data analytics and machine learning workloads in HPC centers brings</span><br>
<span style="background:white">unprecedented need for memory capacity, which is in stark contrast with the</span><br>
<span style="background:white">growing imbalance in the peak compute-to-memory capacity ratio of traditional</span><br>
<span style="background:white">system board based server platforms where memory modules are co-located with</span><br>
<span style="background:white">processors. Meanwhile, traditional simulation workloads leave memory</span><br>
<span style="background:white">underutilized. At the hardware front, the proliferation of heterogeneous,</span><br>
<span style="background:white">special purpose computing elements promotes the need for configurable compute</span><br>
<span style="background:white">platforms, while at the same time, the increasing maturity of optical</span><br>
<span style="background:white">interconnects raises the prospects of better distance independence in</span><br>
<span style="background:white">networking infrastructure.</span><br>
<br>
<span style="background:white">The workshop intends to explore various aspects of resource disaggregation,</span><br>
<span style="background:white">composability and their implications for high performance computing, both in</span><br>
<span style="background:white">dedicated HPC centers as well as in cloud environments.</span><br>
<br>
<br>
<span style="background:white">TOPICS OF INTEREST:</span><br>
<span style="background:white">-------------------</span><br>
<span style="background:white">- Disaggregated hardware in high-performance computing</span><br>
<span style="background:white">- Operating systems and runtime support for disaggregated platforms</span><br>
<span style="background:white">- Simulation of disaggregated platforms with existing infrastructure</span><br>
<span style="background:white">- Runtime systems and programming abstractions for disaggregation and</span><br>
<span style="background:white"> composability</span><br>
<span style="background:white">- Networking for disaggregation, including silicon photonics and optical</span><br>
<span style="background:white"> interconnects</span><br>
<span style="background:white">- Implications of resource disaggregation for scientific computing and</span><br>
<span style="background:white"> HPC applications</span><br>
<span style="background:white">- Algorithm design for disaggregated and composable systems</span><br>
<span style="background:white">- Disaggregated high throughput storage</span><br>
<span style="background:white">- Disaggregated heterogeneous accelerators (GPUs, FPGAs, AI Accelerators, etc.)</span><br>
<span style="background:white">- Resource management in disaggregated and composable platforms</span><br>
<br>
<span style="background:white">TIMELINE AND SUBMISSION PROCEDURE:</span><br>
<span style="background:white">----------------------------------</span><br>
<span style="background:white">Submission deadline: August 11, 2023 (AoE)</span><br>
<span style="background:white">Author notification: September 8, 2023</span><br>
<span style="background:white">Final papers deadline: October 29, 2023</span><br>
<span style="background:white">Workshop date: November 17, 2023</span><br>
<br>
<span style="background:white">The workshop proceedings will be published electronically via the IEEE Computer</span><br>
<span style="background:white">Society Digital Library. Submitted manuscripts should be formatted using</span><br>
<span style="background:white">templates and the CCS2012 guide that are available at:</span><br>
<br>
</span><a href="https://www.acm.org/publications/proceedings-template">https://www.acm.org/publications/proceedings-template</a><span style="color:#1D1D1D"><br>
<br>
<span style="background:white">Regular papers must be between 6 and 12 pages, including references and</span><br>
<span style="background:white">figures, short papers are up to 4 pages, including references and figures.</span><br>
<span style="background:white">Prospective authors should submit their papers in PDF format through</span><br>
<span style="background:white">Linklings? submission site:</span><br>
<br>
</span><a href="https://submissions.supercomputing.org/?page=Submit&id=SC23WorkshopRESDISSubmission&site=sc23">https://submissions.supercomputing.org/?page=Submit&id=SC23WorkshopRESDISSubmission&site=sc23</a><span style="color:#1D1D1D"><br>
<br>
<span style="background:white">WORKSHOP CHAIRS:</span><br>
<span style="background:white">----------------</span><br>
<span style="background:white">Balazs Gerofi Intel Corporation, USA</span><br>
<span style="background:white">John Shalf Lawrence Berkeley National Laboratory, USA</span><br>
<span style="background:white">Christian Pinto IBM Research Europe, Ireland</span><br>
<br>
<br>
<span style="background:white">PROGRAM COMMITTEE (TENTATIVE):</span><br>
<span style="background:white">------------------------------</span><br>
<span style="background:white">Michael Aguilar Sandia National Laboratories, USA</span><br>
<span style="background:white">Paul Carpenter Barcelona Supercomputing Center, Spain</span><br>
<span style="background:white">Larry Dennison Nvidia, USA</span><br>
<span style="background:white">Constantinos Evangelinos IBM Research</span> <br>
<span style="background:white">Madeleine Glick Columbia University, USA</span><br>
<span style="background:white">John (Jack) Lange Oak Ridge National Laboratory, USA</span><br>
<span style="background:white">Ivy Peng KTH Royal Institute of Technology, Sweden</span><br>
<span style="background:white">Yu Tanaka Fujitsu, Japan</span><br>
<span style="background:white">Ga?l Thomas T?l?com SudParis, France</span></span><o:p></o:p></p>
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