[ewg] [PATCH 3/6] nes: Cosmetic changes; support virtual WQs and PPC
Glenn Grundstrom NetEffect
glenn at lists.openfabrics.org
Wed Nov 14 14:25:33 PST 2007
Updated code for the NetEffect NE020 adapter.
Updates include:
- Support for userspace/virtual WQs.
- PowerPC
- Support for multiple debugging levels
- Many, many cosmetic changes inline with kernel.org standards
Diffs for nes_hw.c and nes_hw.h
Signed-off-by: Glenn Grundstrom <ggrundstrom at neteffect.com>
---
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index 09d89a9..d2ab5a7 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -42,6 +42,14 @@
#include "nes.h"
u32 crit_err_count = 0;
+u32 int_mod_timer_init;
+u32 int_mod_cq_depth_256;
+u32 int_mod_cq_depth_128;
+u32 int_mod_cq_depth_32;
+u32 int_mod_cq_depth_24;
+u32 int_mod_cq_depth_16;
+u32 int_mod_cq_depth_4;
+u32 int_mod_cq_depth_1;
#include "nes_cm.h"
@@ -80,6 +88,125 @@ static unsigned char *nes_tcp_state_str[] = {
/**
+ * nes_nic_init_timer_defaults
+ */
+void nes_nic_init_timer_defaults(struct nes_device *nesdev, u8 jumbomode)
+{
+ unsigned long flags;
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
+
+ spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
+
+ shared_timer->timer_in_use_min = NES_NIC_FAST_TIMER_LOW;
+ shared_timer->timer_in_use_max = NES_NIC_FAST_TIMER_HIGH;
+ if (jumbomode) {
+ shared_timer->threshold_low = DEFAULT_JUMBO_NES_QL_LOW;
+ shared_timer->threshold_target = DEFAULT_JUMBO_NES_QL_TARGET;
+ shared_timer->threshold_high = DEFAULT_JUMBO_NES_QL_HIGH;
+ } else {
+ shared_timer->threshold_low = DEFAULT_NES_QL_LOW;
+ shared_timer->threshold_target = DEFAULT_NES_QL_TARGET;
+ shared_timer->threshold_high = DEFAULT_NES_QL_HIGH;
+ }
+
+ /* todo use netdev->mtu to set thresholds */
+ spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
+}
+
+
+/**
+ * nes_nic_init_timer
+ */
+static void nes_nic_init_timer(struct nes_device *nesdev)
+{
+ unsigned long flags;
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
+
+ spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
+
+ if (shared_timer->timer_in_use_old == 0) {
+ nesdev->deepcq_count = 0;
+ shared_timer->timer_direction_upward = 0;
+ shared_timer->timer_direction_downward = 0;
+ shared_timer->timer_in_use = NES_NIC_FAST_TIMER;
+ shared_timer->timer_in_use_old = 0;
+
+ }
+ if (shared_timer->timer_in_use != shared_timer->timer_in_use_old) {
+ shared_timer->timer_in_use_old = shared_timer->timer_in_use;
+ nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
+ 0x80000000 | ((u32)(shared_timer->timer_in_use*8)));
+ }
+ /* todo use netdev->mtu to set thresholds */
+ spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
+}
+
+
+/**
+ * nes_nic_tune_timer
+ */
+static void nes_nic_tune_timer(struct nes_device *nesdev)
+{
+ unsigned long flags;
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
+
+ spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
+
+ if (shared_timer->cq_count>1) {
+ nesdev->deepcq_count += shared_timer->cq_count;
+ if (shared_timer->cq_count <= shared_timer->threshold_low ) { /* increase timer gently */
+ shared_timer->timer_direction_upward++;
+ shared_timer->timer_direction_downward = 0;
+ }
+ else if (shared_timer->cq_count <= shared_timer->threshold_target ) { /* balanced */
+ shared_timer->timer_direction_upward = 0;
+ shared_timer->timer_direction_downward = 0;
+ }
+ else if (shared_timer->cq_count <= shared_timer->threshold_high ) { /* decrease timer gently */
+ shared_timer->timer_direction_downward++;
+ shared_timer->timer_direction_upward = 0;
+ }
+ else if (shared_timer->cq_count <= (shared_timer->threshold_high)*2) {
+ shared_timer->timer_in_use -= 2;
+ shared_timer->timer_direction_upward = 0;
+ shared_timer->timer_direction_downward++;
+ }
+ else {
+ shared_timer->timer_in_use -= 4;
+ shared_timer->timer_direction_upward = 0;
+ shared_timer->timer_direction_downward++;
+ }
+
+ if (shared_timer->timer_direction_upward > 3 ) { /* using history */
+ shared_timer->timer_in_use += 3;
+ shared_timer->timer_direction_upward = 0;
+ shared_timer->timer_direction_downward = 0;
+ }
+ if (shared_timer->timer_direction_downward > 5) { /* using history */
+ shared_timer->timer_in_use -= 4 ;
+ shared_timer->timer_direction_downward = 0;
+ shared_timer->timer_direction_upward = 0;
+ }
+ }
+
+ /* boundary checking */
+ if (shared_timer->timer_in_use > NES_NIC_FAST_TIMER_HIGH) {
+ shared_timer->timer_in_use = NES_NIC_FAST_TIMER_HIGH;
+ }
+ else if (shared_timer->timer_in_use < NES_NIC_FAST_TIMER_LOW) {
+ shared_timer->timer_in_use = NES_NIC_FAST_TIMER_LOW;
+ }
+
+ shared_timer->cq_count = 0;
+
+ spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
+}
+
+
+/**
* nes_init_adapter - initialize adapter
*/
struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
@@ -139,17 +266,8 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
}
nes_init_csr_ne020(nesdev, hw_rev, port_count);
- /* Setup and enable the periodic timer */
- nesdev->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
- if (nesdev->et_rx_coalesce_usecs_irq) {
- nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
- ((u32)(nesdev->et_rx_coalesce_usecs_irq * 8)));
- } else {
- nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
- }
-
max_qp = nes_read_indexed(nesdev, NES_IDX_QP_CTX_SIZE);
- nes_debug(NES_DBG_INIT, "%s: QP_CTX_SIZE=%u\n", __FUNCTION__, max_qp);
+ nes_debug(NES_DBG_INIT, "QP_CTX_SIZE=%u\n", max_qp);
u32temp = nes_read_indexed(nesdev, NES_IDX_QUAD_HASH_TABLE_SIZE);
if (max_qp > ((u32)1 << (u32temp & 0x001f))) {
@@ -197,11 +315,11 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
adapter_size += sizeof(struct nes_qp **) * max_qp;
/* allocate a new adapter struct */
- nesadapter = kmalloc(adapter_size, GFP_KERNEL);
+ nesadapter = kzalloc(adapter_size, GFP_KERNEL);
if (nesadapter == NULL) {
return NULL;
}
- memset(nesadapter, 0, adapter_size);
+
nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
@@ -211,6 +329,7 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
nesadapter->ref_count = 1;
nesadapter->timer_int_req = 0xffff0000;
nesadapter->OneG_Mode = OneG_Mode;
+ nesadapter->doorbell_start = nesdev->doorbell_region;
/* nesadapter->tick_delta = clk_divisor; */
nesadapter->hw_rev = hw_rev;
@@ -227,6 +346,26 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
nesadapter->free_4kpbl = max_4kpbl - 1;
nesadapter->max_pd = num_pds;
nesadapter->arp_table_size = arp_table_size;
+
+ nesadapter->et_pkt_rate_low = NES_TIMER_ENABLE_LIMIT;
+ if (nes_drv_opt & NES_DRV_OPT_DISABLE_INT_MOD) {
+ nesadapter->et_use_adaptive_rx_coalesce = 0;
+ nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
+ nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
+ } else {
+ nesadapter->et_use_adaptive_rx_coalesce = 1;
+ nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
+ nesadapter->et_rx_coalesce_usecs_irq = 0;
+ printk(PFX "%s: Using Adaptive Interrupt Moderation\n", __FUNCTION__);
+ }
+ /* Setup and enable the periodic timer */
+ if (nesadapter->et_rx_coalesce_usecs_irq) {
+ nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
+ ((u32)(nesadapter->et_rx_coalesce_usecs_irq * 8)));
+ } else {
+ nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
+ }
+
nesadapter->base_pd = 1;
nesadapter->device_cap_flags =
@@ -320,6 +459,8 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
spin_lock_init(&nesadapter->resource_lock);
spin_lock_init(&nesadapter->phy_lock);
+ spin_lock_init(&nesadapter->pbl_lock);
+ spin_lock_init(&nesadapter->periodic_timer_lock);
INIT_LIST_HEAD(&nesadapter->nesvnic_list[0]);
INIT_LIST_HEAD(&nesadapter->nesvnic_list[1]);
@@ -473,8 +614,6 @@ int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, u8 One
if (port_count > 1) {
/* init serdes 1 */
- // nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F008);
-
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
if (!OneG_Mode) {
@@ -540,6 +679,8 @@ void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
{
u32 u32temp;
+ nes_debug(NES_DBG_INIT, "port_count=%d\n", port_count);
+
nes_write_indexed(nesdev, 0x000001E4, 0x00000007);
/* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
nes_write_indexed(nesdev, 0x000001E8, 0x00020844);
@@ -563,6 +704,7 @@ void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
nes_write_indexed(nesdev, 0x0000220C, 0x00000001);
nes_write_indexed(nesdev, 0x00002210, 0x000003c1);
nes_write_indexed(nesdev, 0x0000221C, 0x75345678);
+ nes_write_indexed(nesdev, 0x00000908, 0x20000001);
}
if (port_count > 2) {
nes_write_indexed(nesdev, 0x00002400, 0x00000001);
@@ -571,6 +713,7 @@ void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
nes_write_indexed(nesdev, 0x0000240C, 0x00000001);
nes_write_indexed(nesdev, 0x00002410, 0x000003c1);
nes_write_indexed(nesdev, 0x0000241C, 0x75345678);
+ nes_write_indexed(nesdev, 0x00000910, 0x20000001);
nes_write_indexed(nesdev, 0x00002600, 0x00000001);
nes_write_indexed(nesdev, 0x00002604, 0x00000001);
@@ -578,6 +721,7 @@ void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
nes_write_indexed(nesdev, 0x0000260C, 0x00000001);
nes_write_indexed(nesdev, 0x00002610, 0x000003c1);
nes_write_indexed(nesdev, 0x0000261C, 0x75345678);
+ nes_write_indexed(nesdev, 0x00000918, 0x20000001);
}
nes_write_indexed(nesdev, 0x00005000, 0x00018000);
@@ -593,7 +737,7 @@ void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
nes_write_indexed(nesdev, 0x00000900, 0x20000001);
nes_write_indexed(nesdev, 0x000060C0, 0x0000028e);
nes_write_indexed(nesdev, 0x000060C8, 0x00000020);
-
+ //
nes_write_indexed(nesdev, 0x000001EC, 0x5b2625a0);
/* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
@@ -647,10 +791,6 @@ int nes_init_cqp(struct nes_device *nesdev)
u64 u64temp;
u32 u32temp;
-#define NES_NIC_CEQ_SIZE 8
-/* NICs will be on a separate CQ */
-#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
-
/* allocate CQP memory */
/* Need to add max_cq to the aeq size once cq overflow checking is added back */
/* SQ is 512 byte aligned, others are 256 byte aligned */
@@ -671,16 +811,15 @@ int nes_init_cqp(struct nes_device *nesdev)
memset(nesdev->cqp_vbase, 0, nesdev->cqp_mem_size);
/* Allocate a twice the number of CQP requests as the SQ size */
- nesdev->nes_cqp_requests = kmalloc(sizeof(struct nes_cqp_request) *
+ nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
- if (NULL == nesdev->nes_cqp_requests) {
+ if (nesdev->nes_cqp_requests == NULL) {
nes_debug(NES_DBG_INIT, "Unable to allocate memory CQP request entries.\n");
pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
nesdev->cqp.sq_pbase);
return -ENOMEM;
}
- memset(nesdev->nes_cqp_requests, 0, sizeof(struct nes_cqp_request) *
- 2 * NES_CQP_SQ_SIZE);
+
nes_debug(NES_DBG_INIT, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
nesdev->cqp_vbase, (unsigned long)nesdev->cqp_pbase, nesdev->cqp_mem_size);
@@ -744,7 +883,8 @@ int nes_init_cqp(struct nes_device *nesdev)
pmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
cqp_qp_context = vmem;
- cqp_qp_context->context_words[0] = cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
+ cqp_qp_context->context_words[0] =
+ cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
cqp_qp_context->context_words[1] = 0;
cqp_qp_context->context_words[2] = cpu_to_le32((u32)nesdev->cqp.sq_pbase);
cqp_qp_context->context_words[3] = cpu_to_le32(((u64)nesdev->cqp.sq_pbase) >> 32);
@@ -763,12 +903,10 @@ int nes_init_cqp(struct nes_device *nesdev)
NES_IDX_CREATE_CQP_LOW + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
(u32)pmem);
- nes_debug(NES_DBG_INIT, "Address of CQP SQ = %p.\n", nesdev->cqp.sq_vbase);
-
INIT_LIST_HEAD(&nesdev->cqp_avail_reqs);
INIT_LIST_HEAD(&nesdev->cqp_pending_reqs);
- for (count=0; count<2*NES_CQP_SQ_SIZE; count++) {
+ for (count = 0; count < 2*NES_CQP_SQ_SIZE; count++) {
init_waitqueue_head(&nesdev->nes_cqp_requests[count].waitq);
list_add_tail(&nesdev->nes_cqp_requests[count].list, &nesdev->cqp_avail_reqs);
}
@@ -776,12 +914,15 @@ int nes_init_cqp(struct nes_device *nesdev)
/* Write Create CCQ WQE */
cqp_head = nesdev->cqp.sq_head++;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
- cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
+ cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
+ cpu_to_le32(NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
NES_CQP_CQ_CHK_OVERFLOW | ((u32)nesdev->ccq.cq_size << 16));
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
- ((u32)nesdev->ceq_index<<16));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ ((u32)nesdev->ceq_index << 16));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
u64temp = (u64)nesdev->ccq.cq_pbase;
@@ -789,13 +930,10 @@ int nes_init_cqp(struct nes_device *nesdev)
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_PBL_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
u64temp = (u64)&nesdev->ccq;
- cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp>>1));
- cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = cpu_to_le32(((u32)((u64temp)>>33))&0x7FFFFFFF);
- nes_debug(NES_DBG_INIT, "CQ%u context = 0x%08X:0x%08X.\n",
- nesdev->ccq.cq_number,
- le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX]),
- le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX]));
-
+ cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] =
+ cpu_to_le32((u32)(u64temp >> 1));
+ cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
+ cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
/* Write Create CEQ WQE */
@@ -804,8 +942,10 @@ int nes_init_cqp(struct nes_device *nesdev)
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_CEQ +
((u32)nesdev->ceq_index << 8));
cqp_wqe->wqe_words[NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX] = cpu_to_le32(ceq->ceq_size);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
u64temp = (u64)ceq->ceq_pbase;
@@ -818,22 +958,27 @@ int nes_init_cqp(struct nes_device *nesdev)
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_AEQ +
((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
cqp_wqe->wqe_words[NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX] = cpu_to_le32(aeq->aeq_size);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
u64temp = (u64)aeq->aeq_pbase;
cqp_wqe->wqe_words[NES_CQP_AEQ_WQE_PBL_LOW_IDX] = cpu_to_le32((u32)u64temp);
- cqp_wqe->wqe_words[NES_CQP_AEQ_WQE_PBL_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
+ cqp_wqe->wqe_words[NES_CQP_AEQ_WQE_PBL_HIGH_IDX] =
+ cpu_to_le32((u32)(u64temp >> 32));
- /* Write Create CEQ WQE */
+ /* Write Create NIC CEQ WQE */
cqp_head = nesdev->cqp.sq_head++;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_CEQ +
((u32)nesdev->nic_ceq_index << 8));
cqp_wqe->wqe_words[NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX] = cpu_to_le32(nic_ceq->ceq_size);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
u64temp = (u64)nic_ceq->ceq_pbase;
@@ -870,7 +1015,7 @@ int nes_init_cqp(struct nes_device *nesdev)
}
udelay(10);
} while (((nes_read_indexed(nesdev,
- NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
+ NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
/* dump the QP status value */
nes_debug(NES_DBG_INIT, "QP Status = 0x%08X\n", nes_read_indexed(nesdev,
@@ -888,13 +1033,13 @@ int nes_init_cqp(struct nes_device *nesdev)
int nes_destroy_cqp(struct nes_device *nesdev)
{
struct nes_hw_cqp_wqe *cqp_wqe;
- u32 count=0;
+ u32 count = 0;
u32 cqp_head;
unsigned long flags;
- nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP work to complete.\n");
do {
- if (count++ > 1000) break;
+ if (count++ > 1000)
+ break;
udelay(10);
} while (!(nesdev->cqp.sq_head == nesdev->cqp.sq_tail));
@@ -904,46 +1049,51 @@ int nes_destroy_cqp(struct nes_device *nesdev)
/* Disable device interrupts */
nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
- /* Destroy the AEQ */
+
spin_lock_irqsave(&nesdev->cqp.lock, flags);
+
+ /* Destroy the AEQ */
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_AEQ |
- ((u32)PCI_FUNC(nesdev->pcidev->devfn)<<8));
+ ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
+
/* Destroy the NIC CEQ */
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
- ((u32)nesdev->nic_ceq_index<<8));
+ ((u32)nesdev->nic_ceq_index << 8));
+
/* Destroy the CEQ */
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
- (nesdev->ceq_index<<8));
+ (nesdev->ceq_index << 8));
+
/* Destroy the CCQ */
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
- cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
- cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32( nesdev->ccq.cq_number ||
- ((u32)nesdev->ceq_index<<16));
+ cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
+ cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
+ ((u32)nesdev->ceq_index << 16));
+
/* Destroy CQP */
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP |
NES_CQP_QP_TYPE_CQP);
- cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
+ cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
barrier();
- /* Ring doorbell (4 WQEs) */
+ /* Ring doorbell (5 WQEs) */
nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x05800000 | nesdev->cqp.qp_id);
- /* Wait for the destroy to complete */
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
/* wait for the CCQ, CEQ, and AEQ to get destroyed */
@@ -956,7 +1106,7 @@ int nes_destroy_cqp(struct nes_device *nesdev)
}
udelay(10);
} while (((nes_read_indexed(nesdev,
- NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != 0));
+ NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15 << 8)) != 0));
/* dump the QP status value */
nes_debug(NES_DBG_SHUTDOWN, "Function%d: QP Status = 0x%08X\n",
@@ -982,14 +1132,21 @@ int nes_init_phy(struct nes_device *nesdev)
struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 counter = 0;
u32 mac_index = nesdev->mac_index;
+ u32 tx_config;
u16 phy_data;
if (nesadapter->OneG_Mode) {
nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
+ if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) {
+ printk(PFX "%s: Programming mdc config for 1G\n", __FUNCTION__);
+ tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
+ tx_config |= 0x04;
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
+ }
+
nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data);
nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n",
nesadapter->phy_index[mac_index], phy_data);
-
nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
/* Reset the PHY */
@@ -1043,6 +1200,13 @@ int nes_init_phy(struct nes_device *nesdev)
nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300);
+ } else {
+ if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) {
+ /* setup 10G MDIO operation */
+ tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
+ tx_config |= 0x14;
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
+ }
}
return 0;
}
@@ -1085,7 +1249,7 @@ static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
nesnic->rq_head &= nesnic->rq_size - 1;
atomic_dec(&nesvnic->rx_skbs_needed);
barrier();
- if (++rx_wqes_posted==255) {
+ if (++rx_wqes_posted == 255) {
nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
rx_wqes_posted = 0;
}
@@ -1094,7 +1258,7 @@ static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
__FUNCTION__, __LINE__,
atomic_read(&nesvnic->rx_skbs_needed));
if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
- (0 == atomic_read(&nesvnic->rx_skb_timer_running))) {
+ (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
printk("%s[%u] Starting Timer.\n", __FUNCTION__, __LINE__);
atomic_set(&nesvnic->rx_skb_timer_running, 1);
nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
@@ -1143,6 +1307,7 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
u32 cqp_head;
u32 counter;
u32 wqe_count;
+ u8 jumbomode=0;
/* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
nesvnic->nic_mem_size = 256 +
@@ -1227,9 +1392,6 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
/* Send CreateCQ request to CQP */
spin_lock_irqsave(&nesdev->cqp.lock, flags);
cqp_head = nesdev->cqp.sq_head;
- nes_debug(NES_DBG_INIT, "Before filling out cqp_wqe, cqp=%p, sq_head=%u,"
- " sq_tail=%u, cqp_head=%u\n",
- &nesdev->cqp, nesdev->cqp.sq_head, nesdev->cqp.sq_tail, cqp_head);
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
@@ -1238,8 +1400,8 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
((u32)nesvnic->nic_cq.cq_size << 16));
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
u64temp = (u64)nesvnic->nic_cq.cq_pbase;
@@ -1247,9 +1409,9 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_PBL_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
u64temp = (u64)&nesvnic->nic_cq;
- cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp>>1));
+ cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
- cpu_to_le32(((u32)((u64temp)>>33))&0x7FFFFFFF);
+ cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
@@ -1263,7 +1425,7 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
- if (0!= nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE)) {
+ if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0) {
nic_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
}
@@ -1346,13 +1508,19 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
init_timer(&nesvnic->rq_wqes_timer);
nesvnic->rq_wqes_timer.function = nes_rq_wqes_timeout;
nesvnic->rq_wqes_timer.data = (unsigned long)nesvnic;
-#ifdef NES_INT_MODERATE
- nes_debug(NES_DBG_INIT, "Default Interrupt Moderation Enabled\n");
-#endif
#ifdef NES_NAPI
nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
#endif
+ if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
+ {
+ nes_nic_init_timer(nesdev);
+ if (netdev->mtu > 1500) {
+ jumbomode = 1;
+ }
+ nes_nic_init_timer_defaults(nesdev, jumbomode);
+ }
+
return 0;
}
@@ -1381,29 +1549,36 @@ void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
nesvnic->nic.rq_tail &= (nesvnic->nic.rq_size - 1);
}
- /* Destroy NIC QP */
spin_lock_irqsave(&nesdev->cqp.lock, flags);
+
+ /* Destroy NIC QP */
cqp_head = nesdev->cqp.sq_head;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
- cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC);
- cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic_cq.cq_number);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
+ cpu_to_le32(NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC);
+ cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic.qp_id);
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
+
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
/* Destroy NIC CQ */
- cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ |
- ((u32)nesvnic->nic_cq.cq_size << 16));
+ cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
+ cpu_to_le32(NES_CQP_DESTROY_CQ | ((u32)nesvnic->nic_cq.cq_size << 16));
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic_cq.cq_number |
((u32)nesdev->nic_ceq_index << 16));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
@@ -1437,13 +1612,13 @@ void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
nesvnic->nic_pbase);
}
-
#ifdef NES_NAPI
/**
* nes_napi_isr
*/
int nes_napi_isr(struct nes_device *nesdev)
{
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 int_stat;
if (nesdev->napi_isr_ran) {
@@ -1467,7 +1642,10 @@ int nes_napi_isr(struct nes_device *nesdev)
/* Process the CEQs */
nes_process_ceq(nesdev, &nesdev->nesadapter->ceq[nesdev->nic_ceq_index]);
- if (nesdev->et_rx_coalesce_usecs_irq) {
+ if (unlikely((((nesadapter->et_rx_coalesce_usecs_irq) &&
+ (!nesadapter->et_use_adaptive_rx_coalesce)) ||
+ ((nesadapter->et_use_adaptive_rx_coalesce) &&
+ (nesdev->deepcq_count > nesadapter->et_pkt_rate_low)))) ) {
if ((nesdev->int_req & NES_INT_TIMER) == 0) {
/* Enable Periodic timer interrupts */
nesdev->int_req |= NES_INT_TIMER;
@@ -1478,6 +1656,11 @@ int nes_napi_isr(struct nes_device *nesdev)
nes_write32(nesdev->regs+NES_INTF_INT_MASK,
~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
}
+
+ if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
+ {
+ nes_nic_init_timer(nesdev);
+ }
/* Enable interrupts, except CEQs */
nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
} else {
@@ -1485,8 +1668,9 @@ int nes_napi_isr(struct nes_device *nesdev)
nesdev->int_req &= ~NES_INT_TIMER;
nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
+ nesadapter->tune_timer.timer_in_use_old = 0;
}
-
+ nesdev->deepcq_count = 0;
return 1;
} else {
return 0;
@@ -1524,12 +1708,12 @@ void nes_dpc(unsigned long param)
int_stat = nesdev->int_stat;
} else
int_stat = nes_read32(nesdev->regs+NES_INT_STAT);
- if (0 != processed_intf_int) {
+ if (processed_intf_int != 0) {
int_stat &= nesdev->int_req & ~NES_INT_INTF;
} else {
int_stat &= nesdev->int_req;
}
- if (0 == processed_timer_int) {
+ if (processed_timer_int == 0) {
processed_timer_int = 1;
if (int_stat & NES_INT_TIMER) {
timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
@@ -1616,19 +1800,24 @@ void nes_dpc(unsigned long param)
NES_INT_MAC1|NES_INT_MAC2|NES_INT_MAC3;
} while ((int_stat != 0) && (loop_counter++ < MAX_DPC_ITERATIONS));
- if (1 == timer_ints) {
- if (nesdev->et_rx_coalesce_usecs_irq) {
- if (0 == completion_ints) {
+ if (timer_ints == 1) {
+ if ((nesadapter->et_rx_coalesce_usecs_irq) || (nesadapter->et_use_adaptive_rx_coalesce)) {
+ if (completion_ints == 0) {
nesdev->timer_only_int_count++;
- if (nesdev->timer_only_int_count>=NES_TIMER_INT_LIMIT) {
+ if (nesdev->timer_only_int_count>=nesadapter->timer_int_limit) {
nesdev->timer_only_int_count = 0;
nesdev->int_req &= ~NES_INT_TIMER;
nes_write32(nesdev->regs + NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
+ nesdev->nesadapter->tune_timer.timer_in_use_old = 0;
} else {
nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff|(~nesdev->int_req));
}
} else {
+ if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
+ {
+ nes_nic_init_timer(nesdev);
+ }
nesdev->timer_only_int_count = 0;
nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff|(~nesdev->int_req));
}
@@ -1641,7 +1830,11 @@ void nes_dpc(unsigned long param)
nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
}
} else {
- if ((1 == completion_ints) && (nesdev->et_rx_coalesce_usecs_irq)) {
+ if ( (completion_ints == 1) &&
+ (((nesadapter->et_rx_coalesce_usecs_irq) &&
+ (!nesadapter->et_use_adaptive_rx_coalesce)) ||
+ ((nesdev->deepcq_count > nesadapter->et_pkt_rate_low) &&
+ (nesadapter->et_use_adaptive_rx_coalesce) )) ) {
/* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
nesdev->timer_only_int_count = 0;
nesdev->int_req |= NES_INT_TIMER;
@@ -1654,6 +1847,7 @@ void nes_dpc(unsigned long param)
nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
}
}
+ nesdev->deepcq_count = 0;
}
@@ -1690,6 +1884,7 @@ void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq)
} else {
break;
}
+
} while (1);
ceq->ceq_head = head;
@@ -1827,6 +2022,22 @@ void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
phy_data = 0;
nes_debug(NES_DBG_PHY, "PCS says the link is down\n");
}
+ } else if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) {
+ nes_read_10G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index]);
+ temp_phy_data = (u16)nes_read_indexed(nesdev,
+ NES_IDX_MAC_MDIO_CONTROL);
+ u32temp = 20;
+ do {
+ nes_read_10G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index]);
+ phy_data = (u16)nes_read_indexed(nesdev,
+ NES_IDX_MAC_MDIO_CONTROL);
+ if ((phy_data == temp_phy_data) || (!(--u32temp)))
+ break;
+ temp_phy_data = phy_data;
+ } while (1);
+ nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
+ __FUNCTION__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP");
+
} else {
phy_data = (0x0f0f0000 == (pcs_control_status & 0x0f1f0000)) ? 4 : 0;
}
@@ -1878,9 +2089,9 @@ void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq
}
#endif
-// The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
-// getting out of nic_ce_handler
-//
+/* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
+* getting out of nic_ce_handler
+*/
#define MAX_RQES_TO_PROCESS 384
/**
@@ -1892,6 +2103,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
dma_addr_t bus_address;
struct nes_hw_nic *nesnic;
struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
struct nes_hw_nic_rq_wqe *nic_rqe;
struct nes_hw_nic_sq_wqe *nic_sqe;
struct sk_buff *skb;
@@ -1931,7 +2143,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
u64temp = (u64) le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+wqe_fragment_index*2]);
u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+wqe_fragment_index*2]))<<32;
bus_address = (dma_addr_t)u64temp;
- if ((skb) && (skb_headlen(skb) > NES_FIRST_FRAG_SIZE)) {
+ if (test_and_clear_bit(nesnic->sq_tail, nesnic->first_frag_overflow)) {
pci_unmap_single(nesdev->pcidev,
bus_address,
le16_to_cpu(wqe_fragment_length[wqe_fragment_index++]),
@@ -1985,6 +2197,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
if (atomic_read(&nesvnic->rx_skbs_needed) > (nesvnic->nic.rq_size>>1)) {
nes_write32(nesdev->regs+NES_CQE_ALLOC,
cq->cq_number | (cqe_count << 16));
+ nesadapter->tune_timer.cq_count += cqe_count;
cqe_count = 0;
nes_replenish_nic_rq(nesvnic);
}
@@ -1994,12 +2207,10 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
if ((NES_PKT_TYPE_TCPV4_BITS == (pkt_type & NES_PKT_TYPE_TCPV4_MASK)) ||
(NES_PKT_TYPE_UDPV4_BITS == (pkt_type & NES_PKT_TYPE_UDPV4_MASK))) {
- if (0 == (cqe_errv &
- (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR |
- NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
- NES_NIC_ERRV_BITS_IPH_ERR |
- NES_NIC_ERRV_BITS_WQE_OVERRUN))) {
- if (0 == nesvnic->rx_checksum_disabled) {
+ if ((cqe_errv &
+ (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
+ NES_NIC_ERRV_BITS_IPH_ERR | NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
+ if (nesvnic->rx_checksum_disabled == 0) {
rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
}
} else {
@@ -2007,12 +2218,11 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
" errv = 0x%X, pkt_type = 0x%X.\n",
nesvnic->netdev->name, cqe_errv, pkt_type);
}
- } else if (NES_PKT_TYPE_IPV4_BITS == (pkt_type & NES_PKT_TYPE_IPV4_MASK)) {
- if (0 == (cqe_errv &
- (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR |
- NES_NIC_ERRV_BITS_IPH_ERR |
- NES_NIC_ERRV_BITS_WQE_OVERRUN))) {
- if (0 == nesvnic->rx_checksum_disabled) {
+ } else if ((pkt_type & NES_PKT_TYPE_IPV4_MASK) == NES_PKT_TYPE_IPV4_BITS) {
+ if ((cqe_errv &
+ (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_IPH_ERR |
+ NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
+ if (nesvnic->rx_checksum_disabled == 0) {
rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
/* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
nesvnic->netdev->name); */
@@ -2026,8 +2236,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
/* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
- if (NES_PKT_TYPE_APBVT_BITS == (pkt_type & NES_PKT_TYPE_APBVT_MASK)) {
- /* nes_debug(NES_DBG_CQ, "APBVT bit set; Send up NES; nesif_rx\n"); */
+ if ((pkt_type & NES_PKT_TYPE_APBVT_MASK) == NES_PKT_TYPE_APBVT_BITS) {
nes_cm_recv(rx_skb, nesvnic->netdev);
} else {
if (cqe_misc & NES_NIC_CQE_TAG_VALID) {
@@ -2065,6 +2274,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
/* Replenish Nic CQ */
nes_write32(nesdev->regs+NES_CQE_ALLOC,
cq->cq_number | (cqe_count << 16));
+ nesdev->nesadapter->tune_timer.cq_count += cqe_count;
cqe_count = 0;
}
#ifdef NES_NAPI
@@ -2075,9 +2285,11 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
nesvnic->cqes_pending = 0;
break;
}
+#ifndef NES_NAPI
if (rqes_processed > MAX_RQES_TO_PROCESS) {
break;
}
+#endif
} while (1);
cq->cq_head = head;
@@ -2091,6 +2303,11 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
cq->cq_number | (cqe_count << 16));
nes_read32(nesdev->regs+NES_CQE_ALLOC);
#endif
+ if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
+ {
+ nesdev->nesadapter->tune_timer.cq_count += cqe_count;
+ nes_nic_tune_timer(nesdev);
+ }
if (atomic_read(&nesvnic->rx_skbs_needed)) {
nes_replenish_nic_rq(nesvnic);
}
@@ -2153,10 +2370,8 @@ void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
cqp_request,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f);
if (cqp_request->dynamic) {
- atomic_inc(&cqp_reqs_dynfreed);
kfree(cqp_request);
} else {
- atomic_inc(&cqp_reqs_freed);
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
@@ -2168,9 +2383,7 @@ void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f);
if (cqp_request->dynamic) {
kfree(cqp_request);
- atomic_inc(&cqp_reqs_dynfreed);
} else {
- atomic_inc(&cqp_reqs_freed);
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
@@ -2199,7 +2412,6 @@ void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
while ((!list_empty(&nesdev->cqp_pending_reqs)) &&
((((nesdev->cqp.sq_tail+nesdev->cqp.sq_size)-nesdev->cqp.sq_head) &
(nesdev->cqp.sq_size - 1)) != 1)) {
- atomic_inc(&cqp_reqs_redriven);
cqp_request = list_entry(nesdev->cqp_pending_reqs.next,
struct nes_cqp_request, list);
list_del_init(&cqp_request->list);
@@ -2261,18 +2473,16 @@ void nes_process_iwarp_aeqe(struct nes_device *nesdev, struct nes_hw_aeqe *aeqe)
async_event_id = (u16)aeq_info;
tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
- nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p, Tcp state = %d, iWARP state = %d\n",
+ nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p, Tcp state = %s, iWARP state = %s\n",
async_event_id,
le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), aeqe,
- tcp_state, iwarp_state);
- /* nes_tcp_state_str[tcp_state],
- nes_iwarp_state_str[iwarp_state]); */
+ nes_tcp_state_str[tcp_state], nes_iwarp_state_str[iwarp_state]);
switch (async_event_id) {
case NES_AEQE_AEID_LLP_FIN_RECEIVED:
nesqp = *((struct nes_qp **)&context);
- if (atomic_inc_return(&nesqp->close_timer_started)==1) {
+ if (atomic_inc_return(&nesqp->close_timer_started) == 1) {
nesqp->cm_id->add_ref(nesqp->cm_id);
nes_add_ref(&nesqp->ibqp);
schedule_nes_timer(nesqp->cm_node, (struct sk_buff *)nesqp,
@@ -2317,7 +2527,7 @@ void nes_process_iwarp_aeqe(struct nes_device *nesdev, struct nes_hw_aeqe *aeqe)
if ((nesqp->ibqp_state == IB_QPS_RTS) &&
((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) ||
- (async_event_id==NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
+ (async_event_id == NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
switch (nesqp->hw_iwarp_state) {
case NES_AEQE_IWARP_STATE_RTS:
next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING;
@@ -2352,7 +2562,7 @@ void nes_process_iwarp_aeqe(struct nes_device *nesdev, struct nes_hw_aeqe *aeqe)
return;
}
spin_unlock_irqrestore(&nesqp->lock, flags);
- if (async_event_id==NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE) {
+ if (async_event_id == NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE) {
next_iwarp_state = NES_CQP_QP_IWARP_STATE_TERMINATE | 0x02000000;
nesqp->hw_tcp_state = NES_AEQE_TCP_STATE_CLOSED;
nes_debug(NES_DBG_AEQ, "issuing hw modifyqp for QP%u. next state = 0x%08X,"
@@ -2381,7 +2591,7 @@ void nes_process_iwarp_aeqe(struct nes_device *nesdev, struct nes_hw_aeqe *aeqe)
}
if ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) ||
((nesqp->ibqp_state == IB_QPS_RTS)&&
- (async_event_id==NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
+ (async_event_id == NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
nes_add_ref(&nesqp->ibqp);
nes_cm_disconn(nesqp);
} else {
@@ -2572,6 +2782,7 @@ void nes_iwarp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *hw_cq)
return;
}
+
/**
* nes_manage_apbvt()
*/
@@ -2586,8 +2797,8 @@ int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
u16 major_code;
/* Send manage APBVT request to CQP */
- cqp_request = nes_get_cqp_request(nesdev, NES_CQP_REQUEST_NOT_HOLDING_LOCK);
- if (NULL == cqp_request) {
+ cqp_request = nes_get_cqp_request(nesdev);
+ if (cqp_request == NULL) {
nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
return -ENOMEM;
}
@@ -2599,32 +2810,31 @@ int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
accel_local_port, accel_local_port, nic_index);
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_MANAGE_APBVT |
- ((add_port==NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0));
+ ((add_port == NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0));
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] =
cpu_to_le32((nic_index << NES_CQP_APBVT_NIC_SHIFT) | accel_local_port);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
nes_debug(NES_DBG_QP, "Waiting for CQP completion for APBVT.\n");
atomic_set(&cqp_request->refcount, 2);
- nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_NOT_HOLDING_LOCK,
- NES_CQP_REQUEST_RING_DOORBELL);
+ nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
- if (add_port==NES_MANAGE_APBVT_ADD)
- ret = wait_event_timeout(cqp_request->waitq, (0 != cqp_request->request_done),
+ if (add_port == NES_MANAGE_APBVT_ADD)
+ ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
NES_EVENT_TIMEOUT);
nes_debug(NES_DBG_QP, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
ret, cqp_request->major_code, cqp_request->minor_code);
major_code = cqp_request->major_code;
if (atomic_dec_and_test(&cqp_request->refcount)) {
if (cqp_request->dynamic) {
- atomic_inc(&cqp_reqs_dynfreed);
kfree(cqp_request);
} else {
- atomic_inc(&cqp_reqs_freed);
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
@@ -2654,15 +2864,12 @@ void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
nesdev = nesvnic->nesdev;
arp_index = nes_arp_table(nesdev, ip_addr, mac_addr, action);
if (arp_index == -1) {
- /* nes_debug(NES_DBG_NETDEV, "nes_arp_table call returned -1\n"); */
return;
}
- /* nes_debug(NES_DBG_NETDEV, "Update the ARP entry, arp_index=%d\n", arp_index); */
-
/* update the ARP entry */
- cqp_request = nes_get_cqp_request(nesdev, NES_CQP_REQUEST_NOT_HOLDING_LOCK);
- if (NULL == cqp_request) {
+ cqp_request = nes_get_cqp_request(nesdev);
+ if (cqp_request == NULL) {
nes_debug(NES_DBG_NETDEV, "Failed to get a cqp_request.\n");
return;
}
@@ -2674,8 +2881,10 @@ void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(
(u32)PCI_FUNC(nesdev->pcidev->devfn) << NES_CQP_ARP_AEQ_INDEX_SHIFT);
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(arp_index);
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = cpu_to_le32((u32)((u64)(&nesdev->cqp)));
- cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = cpu_to_le32((u32)(((u64)(&nesdev->cqp))>>32));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] =
+ cpu_to_le32((u32)((u64)(&nesdev->cqp)));
+ cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] =
+ cpu_to_le32((u32)(((u64)(&nesdev->cqp)) >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
@@ -2695,8 +2904,7 @@ void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
atomic_set(&cqp_request->refcount, 1);
- nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_NOT_HOLDING_LOCK,
- NES_CQP_REQUEST_RING_DOORBELL);
+ nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
}
@@ -2711,8 +2919,8 @@ void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
struct nes_hw_cqp_wqe *cqp_wqe;
int ret;
- cqp_request = nes_get_cqp_request(nesdev, NES_CQP_REQUEST_NOT_HOLDING_LOCK);
- if (NULL == cqp_request) {
+ cqp_request = nes_get_cqp_request(nesdev);
+ if (cqp_request == NULL) {
nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
return;
}
@@ -2732,22 +2940,19 @@ void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
- nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_NOT_HOLDING_LOCK,
- NES_CQP_REQUEST_RING_DOORBELL);
+ nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
if (wait_completion) {
/* Wait for CQP */
- ret = wait_event_timeout(cqp_request->waitq, (0 != cqp_request->request_done),
+ ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
NES_EVENT_TIMEOUT);
nes_debug(NES_DBG_QP, "Flush SQ QP WQEs completed, ret=%u,"
" CQP Major:Minor codes = 0x%04X:0x%04X\n",
ret, cqp_request->major_code, cqp_request->minor_code);
if (atomic_dec_and_test(&cqp_request->refcount)) {
if (cqp_request->dynamic) {
- atomic_inc(&cqp_reqs_dynfreed);
kfree(cqp_request);
} else {
- atomic_inc(&cqp_reqs_freed);
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
@@ -2755,4 +2960,3 @@ void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
}
}
}
-
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index d4b04f5..67fd2f3 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -33,6 +33,11 @@
#ifndef __NES_HW_H
#define __NES_HW_H
+#define NES_PHY_TYPE_1G 2
+#define NES_PHY_TYPE_IRIS 3
+
+#define NES_MULTICAST_PF_MAX 8
+
enum pci_regs {
NES_INT_STAT = 0x0000,
NES_INT_MASK = 0x0004,
@@ -165,7 +170,7 @@ enum indexed_regs {
NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
};
-#define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
+#define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
#define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
enum nes_cqp_opcodes {
@@ -572,8 +577,8 @@ enum nes_nic_cqe_word_idx {
#define NES_PKT_TYPE_UDPV4_BITS 0x0210
#define NES_PKT_TYPE_UDPV4_MASK 0x3f30
-#define NES_PKT_TYPE_IPV4_BITS 0x0010
-#define NES_PKT_TYPE_IPV4_MASK 0x3f30
+#define NES_PKT_TYPE_IPV4_BITS 0x0010
+#define NES_PKT_TYPE_IPV4_MASK 0x3f30
#define NES_PKT_TYPE_OTHER_BITS 0x0000
#define NES_PKT_TYPE_OTHER_MASK 0x0030
@@ -640,8 +645,6 @@ enum nes_aeqe_tcp_state {
NES_AEQE_TCP_STATE_TIME_WAIT = 11
};
-#define NES_TIMER_INT_LIMIT 2
-
enum nes_aeqe_aeid {
NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102,
NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103,
@@ -731,7 +734,7 @@ enum nes_iwarp_sq_wqe_bits {
};
#define NES_EEPROM_READ_REQUEST (1<<16)
-#define NES_MAC_ADDR_VALID (1<<20)
+#define NES_MAC_ADDR_VALID (1<<20)
/*
* NES index registers init values.
@@ -739,7 +742,7 @@ enum nes_iwarp_sq_wqe_bits {
struct nes_init_values {
u32 index;
u32 data;
- u8 wrt;
+ u8 wrt;
};
/*
@@ -754,10 +757,10 @@ struct nes_pci_regs {
u32 other_regs[59]; /* pad out to 256 bytes for now */
};
-#define NES_CQP_SQ_SIZE 128
-#define NES_CCQ_SIZE 128
-#define NES_NIC_WQ_SIZE 512
-#define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
+#define NES_CQP_SQ_SIZE 128
+#define NES_CCQ_SIZE 128
+#define NES_NIC_WQ_SIZE 512
+#define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
#define NES_NIC_BACK_STORE 0x00038000
struct nes_device;
@@ -803,27 +806,27 @@ struct nes_hw_aeqe {
};
struct nes_cqp_request {
- wait_queue_head_t waitq;
+ wait_queue_head_t waitq;
struct nes_hw_cqp_wqe cqp_wqe;
- struct list_head list;
- atomic_t refcount;
- u16 major_code;
- u16 minor_code;
- u8 waiting;
- u8 request_done;
- u8 dynamic;
- u8 padding[1];
+ struct list_head list;
+ atomic_t refcount;
+ u16 major_code;
+ u16 minor_code;
+ u8 waiting;
+ u8 request_done;
+ u8 dynamic;
+ u8 padding[1];
};
struct nes_hw_cqp {
struct nes_hw_cqp_wqe *sq_vbase;
- dma_addr_t sq_pbase;
- spinlock_t lock;
- wait_queue_head_t waitq;
- u16 qp_id;
- u16 sq_head;
- u16 sq_tail;
- u16 sq_size;
+ dma_addr_t sq_pbase;
+ spinlock_t lock;
+ wait_queue_head_t waitq;
+ u16 qp_id;
+ u16 sq_head;
+ u16 sq_tail;
+ u16 sq_size;
};
#define NES_FIRST_FRAG_SIZE 128
@@ -832,12 +835,13 @@ struct nes_first_frag {
};
struct nes_hw_nic {
- struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
+ struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */
struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
- struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
- struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
+ struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
+ struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
+ unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
dma_addr_t sq_pbase; /* PCI memory for host rings */
dma_addr_t rq_pbase; /* PCI memory for host rings */
@@ -865,7 +869,7 @@ struct nes_hw_nic_cq {
struct nes_hw_qp {
struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */
struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */
- void *q2_vbase; /* PCI memory for host rings */
+ void *q2_vbase; /* PCI memory for host rings */
dma_addr_t sq_pbase; /* PCI memory for host rings */
dma_addr_t rq_pbase; /* PCI memory for host rings */
dma_addr_t q2_pbase; /* PCI memory for host rings */
@@ -876,8 +880,8 @@ struct nes_hw_qp {
u16 rq_head;
u16 rq_tail;
u16 rq_size;
- u8 rq_encoded_size;
- u8 sq_encoded_size;
+ u8 rq_encoded_size;
+ u8 sq_encoded_size;
};
struct nes_hw_cq {
@@ -910,55 +914,93 @@ struct nic_qp_map {
u8 is_hnic;
};
-#define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
+#define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
#define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
#define NES_CQP_APBVT_ADD 0x00008000
#define NES_CQP_APBVT_NIC_SHIFT 16
-#define NES_ARP_ADD 1
-#define NES_ARP_DELETE 2
+#define NES_ARP_ADD 1
+#define NES_ARP_DELETE 2
#define NES_ARP_RESOLVE 3
-#define NES_MAC_SW_IDLE 0
+#define NES_MAC_SW_IDLE 0
#define NES_MAC_SW_INTERRUPT 1
-#define NES_MAC_SW_MH 2
+#define NES_MAC_SW_MH 2
struct nes_arp_entry {
u32 ip_addr;
u8 mac_addr[ETH_ALEN];
};
+#define NES_NIC_FAST_TIMER 96
+#define NES_NIC_FAST_TIMER_LOW 40
+#define NES_NIC_FAST_TIMER_HIGH 1000
+#define DEFAULT_NES_QL_HIGH 256
+#define DEFAULT_NES_QL_LOW 16
+#define DEFAULT_NES_QL_TARGET 64
+#define DEFAULT_JUMBO_NES_QL_LOW 12
+#define DEFAULT_JUMBO_NES_QL_TARGET 40
+#define DEFAULT_JUMBO_NES_QL_HIGH 128
+
+struct nes_hw_tune_timer {
+ u16 cq_count;
+ u16 threshold_low;
+ u16 threshold_target;
+ u16 threshold_high;
+ u16 timer_in_use;
+ u16 timer_in_use_old;
+ u16 timer_in_use_min;
+ u16 timer_in_use_max;
+ u8 timer_direction_upward;
+ u8 timer_direction_downward;
+};
+
+#define NES_TIMER_INT_LIMIT 2
+#define NES_TIMER_INT_LIMIT_DYNAMIC 10
+#define NES_TIMER_ENABLE_LIMIT 4
+
struct nes_adapter {
- u32 hw_rev;
- u64 fw_ver;
+ u64 fw_ver;
+ unsigned long *allocated_qps;
+ unsigned long *allocated_cqs;
+ unsigned long *allocated_mrs;
+ unsigned long *allocated_pds;
+ unsigned long *allocated_arps;
+ struct nes_qp **qp_table;
+ struct workqueue_struct *work_q;
+ struct list_head list;
+ struct list_head active_listeners;
+ /* list of the netdev's associated with each logical port */
+ struct list_head nesvnic_list[4];
+
+ struct timer_list mh_timer;
+ struct work_struct work;
+ spinlock_t resource_lock;
+ spinlock_t phy_lock;
+ spinlock_t pbl_lock;
+ spinlock_t periodic_timer_lock;
+
+ struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
+
+ /* Adapter CEQ and AEQs */
+ struct nes_hw_ceq ceq[16];
+ struct nes_hw_aeq aeq[8];
+
+ struct nes_hw_tune_timer tune_timer;
+
+ unsigned long doorbell_start;
+
+ u32 hw_rev;
u32 vendor_id;
u32 vendor_part_id;
- struct nes_qp **qp_table;
u32 device_cap_flags;
u32 tick_delta;
u32 timer_int_req;
- /* RNIC Resource Lists */
- unsigned long *allocated_qps;
- unsigned long *allocated_cqs;
- unsigned long *allocated_mrs;
- unsigned long *allocated_pds;
- struct list_head active_listeners;
- spinlock_t resource_lock;
- spinlock_t phy_lock;
-
- /* arp table */
- unsigned long *allocated_arps;
- struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
- u32 arp_table_size;
- u32 next_arp_index;
+ u32 arp_table_size;
+ u32 next_arp_index;
- /* Adapter CEQ and AEQs */
- struct nes_hw_ceq ceq[16];
- struct nes_hw_aeq aeq[8];
-
- /* RNIC Limits */
u32 max_mr;
u32 max_256pbl;
u32 max_4kpbl;
@@ -993,61 +1035,69 @@ struct nes_adapter {
u32 nic_rx_eth_route_err;
+ u32 et_rx_coalesce_usecs;
+ u32 et_rx_max_coalesced_frames;
+ u32 et_rx_coalesce_usecs_irq;
+ u32 et_rx_max_coalesced_frames_irq;
+ u32 et_pkt_rate_low;
+ u32 et_rx_coalesce_usecs_low;
+ u32 et_rx_max_coalesced_frames_low;
+ u32 et_pkt_rate_high;
+ u32 et_rx_coalesce_usecs_high;
+ u32 et_rx_max_coalesced_frames_high;
+ u32 et_rate_sample_interval;
+ u32 timer_int_limit;
+
/* Adapter base MAC address */
- u16 mac_addr_high;
u32 mac_addr_low;
+ u16 mac_addr_high;
u16 firmware_eeprom_offset;
u16 software_eeprom_offset;
u16 max_irrq_wr;
+ /* pd config for each port */
+ u16 pd_config_size[4];
+ u16 pd_config_base[4];
+
+ /* the phy index for each port */
+ u8 phy_index[4];
+ u8 mac_sw_state[4];
+ u8 mac_link_down[4];
+ u8 phy_type[4];
+
/* PCI information */
- unsigned int devfn;
+ unsigned int devfn;
unsigned char bus_number;
unsigned char OneG_Mode;
- struct list_head list;
- /* list of the netdev's associated with each logical port */
- struct list_head nesvnic_list[4];
-
unsigned char ref_count;
- u8 netdev_count;
- u8 netdev_max; /* from host nic address count in EEPROM */
- u8 port_count;
-
- /* the phy index for each port */
- u8 phy_index[4];
- u8 mac_sw_state[4];
- u8 mac_link_down[4];
- u8 ports[4];
-
- struct timer_list mh_timer;
- /* wait_queue_head_t wait_q; */
- struct work_struct work;
- struct workqueue_struct *work_q;
- /* u32 worker_quit; */
-
- void *cm_context;
+ u8 netdev_count;
+ u8 netdev_max; /* from host nic address count in EEPROM */
+ u8 port_count;
+ u8 virtwq;
+ u8 et_use_adaptive_rx_coalesce;
};
struct nes_pbl {
- u64 *pbl_vbase;
- dma_addr_t pbl_pbase;
- unsigned long user_base;
- u32 pbl_size;
+ u64 *pbl_vbase;
+ dma_addr_t pbl_pbase;
+ struct page *page;
+ unsigned long user_base;
+ u32 pbl_size;
struct list_head list;
/* TODO: need to add list for two level tables */
};
struct nes_listener {
- struct work_struct work;
+ struct work_struct work;
struct workqueue_struct *wq;
- struct nes_vnic *nesvnic;
- struct iw_cm_id *cm_id;
- struct list_head list;
- unsigned long socket;
- u8 accept_failed;
+ struct nes_vnic *nesvnic;
+ struct iw_cm_id *cm_id;
+ struct list_head list;
+ unsigned long socket;
+ u8 accept_failed;
};
struct nes_ib_device;
@@ -1070,39 +1120,39 @@ struct nes_vnic {
struct nes_device *nesdev;
struct net_device *netdev;
struct vlan_group *vlan_grp;
- atomic_t rx_skbs_needed;
- atomic_t rx_skb_timer_running;
- int budget;
- int rx_cqes_completed;
- int cqe_allocs_pending;
- u32 msg_enable;
+ atomic_t rx_skbs_needed;
+ atomic_t rx_skb_timer_running;
+ int budget;
+ int rx_cqes_completed;
+ int cqe_allocs_pending;
+ u32 msg_enable;
/* u32 tx_avail; */
- __be32 local_ipaddr;
-
- spinlock_t tx_lock; /* could use netdev tx lock? */
- struct timer_list rq_wqes_timer;
- u32 nic_mem_size;
- void *nic_vbase;
- dma_addr_t nic_pbase;
- struct nes_hw_nic nic;
+ __be32 local_ipaddr;
+
+ spinlock_t tx_lock; /* could use netdev tx lock? */
+ struct timer_list rq_wqes_timer;
+ u32 nic_mem_size;
+ void *nic_vbase;
+ dma_addr_t nic_pbase;
+ struct nes_hw_nic nic;
struct nes_hw_nic_cq nic_cq;
struct net_device_stats netstats;
/* used to put the netdev on the adapters logical port list */
struct list_head list;
u16 max_frame_size;
- u8 netdev_open;
- u8 linkup;
- u8 logical_port;
- u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
- u8 perfect_filter_index;
- u8 nic_index;
- u8 qp_nic_index[4];
- u8 next_qp_nic_index;
- u8 of_device_registered;
- u8 rdma_enabled;
- u8 cqes_pending;
- u8 rx_checksum_disabled;
+ u8 netdev_open;
+ u8 linkup;
+ u8 logical_port;
+ u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
+ u8 perfect_filter_index;
+ u8 nic_index;
+ u8 qp_nic_index[4];
+ u8 next_qp_nic_index;
+ u8 of_device_registered;
+ u8 rdma_enabled;
+ u8 cqes_pending;
+ u8 rx_checksum_disabled;
};
struct nes_ib_device {
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