[openib-general] [PATCH] mthca updates (2.6.8 dependent)

[Michael S. Tsirkin]

Hello!
Quoting r. Roland Dreier (roland at topspin.com) "Re: [openib-general] [PATCH] mthca updates (2.6.8 dependent)":
>     Michael> I'm not sure you can rely on messages being ordered
>     Michael> properly with regard to posted writes e.g. inside the
>     Michael> chipset.
> 
> Hmm... that seems like a really ugly "feature" to allow interrupts to
> pass posted writes within the chipset.

No, I was talking about interrupt messages in PCI Express.

> In any case in mthca I unconditionally rearm the EQ after polling it,
> so I think my MSI-X implementation should work OK even if we have that
> ordering problem.

Should be OK then, the only reason you have to read ECR is to know
which EQs to arm. If you know it from MSI-X Vector, ordering will take
care of itself.

MST