[openib-general] [PATCH] mthca updates (2.6.8 dependent)

[Roland Dreier]

    Grant> MSI is useful with one if the driver can avoid all MMIO
    Grant> read in the normal interrupt case. MSI guarantees strong
    Grant> ordering of DMA to host mem and delivery of the interrupt.

I agree that MSI messages are strongly ordered with respect to other
writes coming from a device.  However, I couldn't find anything
explicit in the PCI spec that says that the interrupt can't pass an
earlier write to memory once the MSI hits the host bridge.  In other
words the interrupt message will definitely hit the chipset after any
writes that were initiated before it, but I didn't see anywhere it's
guaranteed that the CPU will see those writes before it sees the
interrupt.

The Intel E7500 Xeon chipset PCI bridge datasheet does say that an
interrupt message causes the bridge to flush its write buffers to
preserve precisely this ordering, but I don't know whether everyone
followed or will follow this example (I'm sure we'll see many more MSI
implementations on PCI Express).

 - R.