[openib-general] ia64 perf and FMR

[Grant Grundler]

On Sun, Apr 03, 2005 at 11:16:35PM -0700, Fab Tillier wrote:
> If you have access to a Tavor PRM, you can see what they are and how they
> work.  The Mellanox implementation of FMR is not the same as FMR defined in
> the 1.2 IB spec.

I know who in HP does.  But I hate contaminating myself with docs
that are only available under NDA. That's why I haven't looked at
them yet.  Is "competitive advantage" still a reason for Mellanox
to NOT publish the PRM for older PCI-X chips?
(e.g. Tavor)

> Basically, FMR lets you register memory without using the command interface,
> using memory mapped HCA resource to access the translation tables directly.
> There are pitfalls with them related to the HCA caching translation entries
> and cache coherency between the HCA and what the app wants it to do.

ok - I can see how FMR helps with latency and PCI bus utilization.
But not a 2x increase in throughput.

> That's my current understanding, and will gladly stand corrected.  I hope
> that helps some.

It does.

thanks,
grant