[openib-general] [PATCH] roland-uverbs: possible race condition

[Roland Dreier]

    Michael> This is a platform / chipset issue and not a PCIe
    Michael> protocol / specification issue since the problem is
    Michael> outside the scope of the root complex / root port
    Michael> (RC/RP).

In that case a driver cannot rely on ordering for PCIe INTx messages
and and must do something like an MMIO read to ensure that the
interrupt has not passed any other writes.  The fact that the spec
seems silent on this point makes me believe this is in fact the case.
Note that this is quite different from MSI/MSI-X, where I see language
in the MSI-X ECN placing ordering requirements on the platform:

    An MSI or MSI-X message, by virtue of being a posted memory write
    (PMW) transaction, is prohibited by PCI ordering rules from
    passing PMW transactions sent earlier by the function. The system
    must guarantee that an interrupt service routine invoked as a
    result of a given message will observe any updates performed by
    PMW transactions arriving prior to that message. Thus, the
    interrupt service routine of a device driver is not required to
    read from a device register in order to ensure data consistency
    with previous PMW transactions.

Since there seems to be no analogous statement about INTx messages in
the PCIe spec, there is no guarantee that an ISR will see all PMW
transactions issued prior to the INTx message.

Thanks,
  Roland