[openib-general] ip over ib throughtput

[Roland Dreier]

    Grant> Some ZX1 docs have recently been published but I don't know
    Grant> if any of that specifically covers MSI:

According to http://ftp.parisc-linux.org/docs/chips/zx1-mio.pdf,
section 3.4.4.1:

    A message singled interrupt (MSI) transaction occurs when a I/O
    device does a Memory Write transaction to the 1MB address range
    starting at 0xFEE0_0000 (zx1 ioa makes MSI space
    programmable). The rope guest claims the transaction and forwards
    them to the zx1 mio as interrupt address and interrupt data. The
    transaction makes its way to the Itanium-2 bus just like a P2P
    write. The zx1 mio eventually does an interrupt transaction on the
    Itanium-2 bus with the same address and data, but using the
    Itanium-2 bus encoding for an interrupt transaction.

The kernel does use an address in the 0xfee region, so that's OK.  I
assume the contents are OK as well, since the doc seems to be saying
that ZX1 mio does no translation.  So I'm not sure what might be going
wrong.

I don't think this is an mthca issue, since the MSI-X API is pretty
hard to get wrong.  Do you have any other devices that can generate
MSIs?  tg3 devices should be MSI capable, I'm not sure if anyone has
hacked the driver to turn it on, but if tg3 doesn't work either then
that definitely points to a core platform PCI driver issue.

 - R.