[openib-general] has anyone tried MSI-X on Opteron?

[Roland Dreier]

    Eric> I just did a quick look at the hypertransport spec.  The
    Eric> mapping from MSI/MSI-X interrupts to native hypertransport
    Eric> interrupts was defined in rev 1.05 which post-dates the 8131
    Eric> by a little but but it is certainly newer than the more
    Eric> recent chips.

Thanks for the pointer.  I looked at section 7.12 of the 1.05 HT spec,
which defines the MSI mapping.  The default MSI address range of
0xFEE_xxxxx does match the Intel-type APIC addresses that the Linux
MSI code will program devices with.  However, lspci shows that the
8131 in my systems have no such MSI HT capability block.

If anyone has an nForce4 mobo, I would be _very_ interested to see the
output of lspci -vvxxx, especially using lspci from the latest
pciutils 2.1.99 (available from /pub/software/utils/pciutils/alpha on
ftp.kernel.org).

    Eric> Given that hypertransport interrupts are simply encoded as
    Eric> posted write packets it may be possible to send an
    Eric> appropriate interrupt even without explicit bridge support.

I would be quite surprised if you could generate a PCI write cycle
that gets turned into an HT interrupt message without the bridge
supporting MSI.  It seems to me that any write cycle is either going
to get turned into an upstream HT write if it is to a valid address,
or get dropped or hose the system if it's to an invalid address.

Thanks,
  Roland