[openib-general] has anyone tried MSI-X on Opteron?

[Michael S. Tsirkin]

Hello!
Quoting r. Eric W. Biederman (ebiederman at lnxi.com) "Re: [openib-general] has anyone tried MSI-X on Opteron?":
> Roland Dreier <roland at topspin.com> writes:
> 
> >     Eric> Given that hypertransport interrupts are simply encoded as
> >     Eric> posted write packets it may be possible to send an
> >     Eric> appropriate interrupt even without explicit bridge support.
> > 
> > I would be quite surprised if you could generate a PCI write cycle
> > that gets turned into an HT interrupt message without the bridge
> > supporting MSI.  It seems to me that any write cycle is either going
> > to get turned into an upstream HT write if it is to a valid address,
> > or get dropped or hose the system if it's to an invalid address.
> 
> A HT interrupt message is a write cycle to a an address in the range
> 0xFDF8000000 -  0xFDF8FFFFFF.  So a PCI write cycle getting turned
> into a HT write cycle is useful behavior.  The question is can we
> generate an appropriate write to those addresses from the card.

Sure, just program the MSI register to these values, and patch the
driver to apply MSI and not regular interrupt to the EQs.

mst