[openib-general] [PATCH] roland-uverbs: possible race condition

[Michael S. Tsirkin]

Quoting r. Roland Dreier <roland at topspin.com>:
> Subject: Re: [openib-general] [PATCH] roland-uverbs: possible race condition
> 
>     Michael> 1. In MSI-X, since the interrupt is specific for this EQ,
>     Michael> we know that the EQ wont be empty when we poll it.  In
>     Michael> any case, (even if you believe we may get an extra MSI-X
>     Michael> interrupt in rare cases) , an extra set ci + arm do no
>     Michael> harm.
> 
>     Michael> Thus in my opinion the check is not needed (but does no
>     Michael> actual harm).
> 
> I think I agree with this.
> 
>     Michael> 2. In regular interrupt: I think I see a race condition.
>     Michael> We must always arm an eq - even if it is found empty.
>     Michael> This is because the interrupt may bypass an EQ entry
>     Michael> write to memory. Thus the EQ will be empty when we poll
>     Michael> it, but on the other hand if we do not arm the EQ, we
>     Michael> will never get another interrupt.
> 
> I'm not sure I believe this for either Tavor or Arbel.  For Tavor, we
> read the ECR via MMIO, and I don't think its possible for the read
> response for the ECR value to pass the write of the EQ entry from the
> HCA.

Ah, right.

> For Arbel, even a legacy interrupt on PCI Express is carried by
> a message and I don't think that message can pass the EQE write.
True while on the Express, but I think for the chipset it is
legal to order interrupt messages differently from writes.

> So
> I'm not convinced most of this patch is necessary.
> 
>  - R.
> 

OK, I'll split it up and resend so you can apply parts of it.
-- 
MST - Michael S. Tsirkin