[openib-general] basic IB doubt

[glebn at voltaire.com]

On Sun, Aug 27, 2006 at 03:30:56PM -0700, Roland Dreier wrote:
>     glebn> So, before touching the data that was RDMAed into the
>     glebn> buffer application should cache invalidate the buffer, is
>     glebn> this even possible from user space? (Not on x86, but it
>     glebn> isn't needed there.)
> 
> Yes, on any architecture that is not cache-coherent with PCI DMA, some
> cache invalidation/flushing will be necessary.  And this probably
> won't be possible from userspace if the cache is physically tagged.
> (Are there any such architectures in real use, ie non-coherent with
> PCI and physically tagged cache?)
> 
AFAIR at least PPC603 with bus snooping disabled is such architecture.
But the point is in order to write really portable code you can't just
assume cache coherency, so data receive order is not the only assumption
we are making currently.

--
			Gleb.