[openib-general] [PATCHv2] mthca: speed up memory registration by filling MTTs directly

[Michael S. Tsirkin]

> and in fact not even that would work: since a non-cache-coherent CPU
> can only work on cacheline-sized chunks there's no safe way to touch the MTT
> table.

Roland, could you please clarify what did you mean by this statement?

With current code firmware might be doing WRITE_MTT while CPU is writing to the
same cache line, and I expect this might confuse things, but it seems that with
my fmr/mr merge patch, we never have both CPU and firmware write to the same
MTTs entries.

So, assuming my patch is applied why isn't sticking pci_dma_sync_sg in FMR code
sufficient?

-- 
MST