[openib-general] [PATCHv2] mthca: speed up memory registration by filling MTTs directly

[Roland Dreier]

 > > With current code firmware might be doing WRITE_MTT while CPU is writing to the
 > > same cache line, and I expect this might confuse things, but it seems that with
 > > my fmr/mr merge patch, we never have both CPU and firmware write to the same
 > > MTTs entries.
 > > 
 > > So, assuming my patch is applied why isn't sticking pci_dma_sync_sg in FMR code
 > > sufficient?

Yes, assuming that the CPU is the only entity ever writing to the MTT
table, then doing pci_dma_sync_sg_for_cpu() before writing and
pci_dma_sync_sg_for_device() afterwards should be OK.  I think.

 > Documentation/DMA-mapping.txt actually says:
 > 
 > > Without that, you'd see cacheline
 > > sharing problems (data corruption) on CPUs with DMA-incoherent caches.
 > > (The CPU could write to one word, DMA would write to a different one
 > >  in the same cache line, and one of them could be overwritten.)

Not sure what the relevance of that is -- it's kind of making the
opposite point, that you need to make sure the CPU never touches a
cacheline that might be DMAed at the same point.  The part you snipped
mentions alignment problems.

What saves us for the MTT table is that with your patch the device
never writes to the MTT table at all.

 - R.