[openib-general] Drop in performance on Mellanox MT25204 single port DDR HCA
Michael Krause
krause at cup.hp.com
Tue Oct 3 13:26:08 PDT 2006
At 02:43 PM 10/2/2006, Roland Dreier wrote:
> Robert> Yes. 1250Mbytes/sec is what we expect. You say the 128
> Robert> value comes from the BIOS ? If so, we need to discuss this
> Robert> with our BIOS team to find out why they limit it to 128,
> Robert> perhaps it is a BIOS bug.
>
>Yes, I believe that the BIOS is the only place that would set that
>value. We know that resetting the device makes it go back to a
>different default value, and nothing in the kernel that I know of is
>going to set it down to 128.
128B is the default minimum from PCIe so likely some BIOS engineer took a
conservative view and chose the defaults (go figure). Setting Max Read
Request Size = 4096 is preferred on any implementation as it is basically
free from a chipset perspective. The chipset will likely return in cache
line quantities but there is some obvious optimizations to be achieved by
issuing a single DMA Read Request.
Mike
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