[openib-general] Race in mthca_cmd_post()

[Roland Dreier]

 > 23454:    Config Write     REG = 01 TYPE = 1    BE = 0000  Req = (0,0,0)  Tag = 1  Bus = 1 Device = 0 Function = 0     WAIT = 2
 > 23462:    Memory Rd DW     A = 00280698  BE = 0000  Req = (0,0,0)  Tag = 0      WAIT = 2
 > 23470:    Split compl.     Lower A = 00  Req = (0,0,0)  Tag = 0  Comp = (0,2,0)     WAIT = 1   (Error completion)
 > 23476:    Split compl.     Lower A = 00  Req = (0,0,0)  Tag = 1  Comp = (0,2,0)     WAIT = 1   (Normal completion of WRITE)
 > 
 > We see here that a Config Write to Reg 01 (PCI_COMMAND) is issued across the
 > bus. We then see the Memory Read to 698 that goes across the bus before the
 > completion of the Config Write to Reg 01.

OK, this is the crux of my confusion.  I always thought (and the PCI
spec seems to say this too) that config writes are non-posted, which
means that the Config Write cycle in your trace should block
everything until it is completed.  Is that not true?  Or could this be
a bug in the SAL for this platform or something like that?

 - R.