[ofa-general] [PATCH 4/5] [uDAPL v2] dapl scm: change IB RC qp inline and timer defaults

Arlin Davis arlin.r.davis at intel.com
Thu Aug 14 17:06:56 PDT 2008


rnr nak can be the result of any operation not just
message send receiver not ready. Timer is much too
large given this case. Adjust inline send.

Signed-off by: Arlin Davis ardavis at ichips.intel.com
---
 dapl/openib_scm/dapl_ib_util.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/dapl/openib_scm/dapl_ib_util.h b/dapl/openib_scm/dapl_ib_util.h
index bd702a9..4e75d2c 100644
--- a/dapl/openib_scm/dapl_ib_util.h
+++ b/dapl/openib_scm/dapl_ib_util.h
@@ -186,16 +186,16 @@ typedef struct ibv_comp_channel *ib_wait_obj_handle_t;
 #define IB_INVALID_HANDLE	NULL
 
 /* inline send rdma threshold */
-#define	INLINE_SEND_DEFAULT	128
+#define	INLINE_SEND_DEFAULT	200
 
 /* qkey for UD QP's */
 #define SCM_UD_QKEY	0x78654321
 
 /* RC timer - retry count defaults */
-#define SCM_ACK_TIMER 15	/* 5 bits, 4.096us*2^ack_timer. 15 == 134ms */
-#define SCM_ACK_RETRY 7		/* 3 bits, 7 * 134ms = 940ms */
-#define SCM_RNR_TIMER 28	/* 5 bits, 28 == 163ms, 31 == 491ms */
-#define SCM_RNR_RETRY 7		/* 3 bits, 7 == infinite */
+#define SCM_ACK_TIMER 16 /* 5 bits, 4.096us*2^ack_timer. 16== 268ms */
+#define SCM_ACK_RETRY 7  /* 3 bits, 7 * 268ms = 1.8 seconds */
+#define SCM_RNR_TIMER 12 /* 5 bits, 12 =.64ms, 28 =163ms, 31 =491ms */
+#define SCM_RNR_RETRY 7  /* 3 bits, 7 == infinite */
 #define SCM_IB_MTU    1024
 
 /* Global routing defaults */
-- 
1.5.2.5





More information about the general mailing list