[openib-general] [PATCH] mthca updates (2.6.8 dependent)

[Dror Goldenberg]

> -----Original Message-----
> From: Grant Grundler [mailto:iod00d at hp.com] 
> Sent: Tuesday, August 31, 2004 7:00 AM
> 
> On Mon, Aug 16, 2004 at 09:27:13PM +0300, Dror Goldenberg wrote:
> > In PCI/PCIX, the interrupt is a wire, so it is not 

> 
> Dror,
> I'm pretty sure you understand the issues but are using confusing
> terminology:
> o posted write. CPU does not wait for completion of write to 
> IO device o PIO write. Programmed IO - CPU write to IO 
> device. May or not be posted
> 	and typically depends on chipset and which "space" (MMIO vs I/O
> 	Port) is the target.
> o PIO read.  Programmed IO - CPU read stalls until completion 
> (may be MMIO
>       or I/O port space).
> o DMA write: IO Device write to host memory (aka upstream)
> o DMA read: Device command to retrieve data from host memory 
> (downstream) o DMA read return: completion portion of DMA 
> read command (upstream)
> 
> A PIO Read "flushes" inflight DMA writes from a CPU 
> perspective because the CPU stalls until the PIO read completes.
> 

Yes... it sounds much better. Thanks !


> > In PCI-Express, the interrupt is a message, so it will work. The 
> > interrupt will just flush the data to the memory because it 
> maintain 
> > ordering with posted writes upstream.
> 
> The MSI/MSI-X interrupt doesn't do anything.
> The interrupt transaction is just another DMA Write and must 
> follow the PCI ordering rules like any other DMA write. The 
> destination address is just not a regular host memory location.

I was talking about regular interrupts in PCI express. For PCI express
MSI/MSI-X are plain DMA writes. However, good old interrupts in PCI
express don't go on external wire. They just go on the same bus like 
the data, for that they use special PCI express messages. And, they
maintain ordering like other any other DMA writes. So, although the
same semantics of "old interrupts" is preserved, the behavior is a bit
different in PCI express
 
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