[openib-general] basic IB doubt

[Jason Gunthorpe]

On Mon, Aug 28, 2006 at 01:49:27PM -0400, Talpey, Thomas wrote:

> Okay, that's good. However, doesn't it delay reads and writes until the
> necessary table walk / mapping is resolved? Because it passes all other
> cycles through, it seems to me that an interrupt may pass data, meaning
> that ordering (at least) may be somewhat different when it's present.
> And, those pending writes are not in the cache's consistency domain
> (i.e. they can't be snooped yet, right?).

I've never asked AMD this kind of question directly, but my guess
would be that either the HT queues or the SRQ stalls while the table
walk is performed and that maintains the in-order requirements of
PCI/HT. Otherwise, like you say, the ordering guarentees of MSI could
be lost..

Jason