[ofa-general] post_recv question

[Roland Dreier]

 > I think we can assume that the ringing of the doorbell is synchronous,
 > i.e. when the processor completes it's write, the card knows there are
 > RQ WQE available in host memory, 

It doesn't affect your larger point, but to be pedantically precise,
writes across PCI will be posted, so the CPU may fully retire a write
to MMIO long before that write completes at its final destination.

 - R.