[ofa-general] post_recv question

[Tom Tucker]

On 2/22/08 12:09 AM, "Roland Dreier" <rdreier at cisco.com> wrote:

>> I think we can assume that the ringing of the doorbell is synchronous,
>> i.e. when the processor completes it's write, the card knows there are
>> RQ WQE available in host memory,
> 
> It doesn't affect your larger point, but to be pedantically precise,
> writes across PCI will be posted, so the CPU may fully retire a write
> to MMIO long before that write completes at its final destination.
> 

You're right. In fact, I think up to 4 words for the common implementation.
But I think this speaks again to the claim that guarantees between adapters
on different busses can't work because posted writes go to different FIFO's.

>  - R.