[nvmewin] quick update on perf investigation

[Luse, Paul E]

As a follow-up, I ran overnight w/no issues with the one change where I dedicate core 0 completions to admin only (still conditional on Chatham).  Smells like a hw/fw problem at this point but anyway I added a compile switch to allow us to choose between ISR completions and DPC completions and sure enough things work fine now with ISR completions (no watchdog issues which is what led to the DPC implementation).  I think it makes sense to leave them both in there (default is ISR completions for now) so foks can profile on their own HW and decide which is right for them.  I'll try to run some xperf traces before the Tue meeting and bring some data describing the difference; from the pue iometer perspective using ISR our CPU util goes down from ~20 to about ~18 on the average, I suspect its because we're not masking MSIX ints therefore when using DPCs our ISR gets called a zillion times where the DPC doesn't get scheduled because there's one outstanding already; that overhead of course goes away but its not clear what the system level cost is of spending more time at DIRQL vs more time attempting to schedule DPCs

Thx
Paul

____________________________________
Paul Luse
Sr. Staff Engineer
PCG Server Software Engineering
Desk: 480.554.3688, Mobile: 480.334.4630

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