[ofiwg] packet ordering considerations.

Paul Grun grun at cray.com
Tue Jun 24 10:13:30 PDT 2014

We do have some hardware designers in the group (me among them, although I'm not a memory controller designer).  But the problem is that we probably should not be designing an architecture that is dependent on any particular hardware implementation.  That is definitely true for the memory controller design, since those are very much specific to any particular vendor.  It's somewhat less true for PCIe designs since the PCIe semantics are driven by an industry standard specification.  We are not insulated from a decision by the PCIe SIG to change the semantics, but that seems a lot less risky than relying on the memory controller design.

From: ofiwg-bounces at lists.openfabrics.org [mailto:ofiwg-bounces at lists.openfabrics.org] On Behalf Of Geoffrey Paulsen
Sent: Tuesday, June 24, 2014 10:08 AM
To: ofiwg at lists.openfabrics.org
Subject: [ofiwg] packet ordering considerations.

Are there any PCI experts or memory controller experts in the working group?  As an MPI engineer, I don't know enough about ordering considerations at the lower physical layer to comment intelligently about this topic.  As things become more asyncronus, we don't want to be fighting the memory controllers, or the busses on ordering issues.


Geoffrey (Geoff) Paulsen
Software Engineer - Platform MPI


Phone: 1-720-349-2832
E-mail: gpaulsen at us.ibm.com<mailto:gpaulsen at us.ibm.com>


1177 S Belt Line Rd
Coppell, TX 75019-4642
United States

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