[ofw] [PATCH] affinity options

[Sean Hefty]

Ok - so the affinity is a bitmask?  0 means default, 1 is 1st processor, 2 is
2nd, 4 is 3rd?  Is this correct?

 

I still don't understand if there's a special reason to get the last CPU.

 

  _____  

From: Slava Strebkov [mailto:slavas at voltaire.com] 
Sent: Monday, April 07, 2008 11:02 PM
To: Hefty, Sean; Leonid Keller; ofw at lists.openfabrics.org
Subject: RE: [ofw] [PATCH] affinity options

 

Zero (0) specifies a system default affinity - the default choice.

Last CPU mask has been chosen for customers to override default system affinity
and bind interrupt to last CPU without calculating bitmask.

 

 

 

  _____  

From: Sean Hefty [mailto:sean.hefty at intel.com] 
Sent: Monday, April 07, 2008 9:22 PM
To: 'Leonid Keller'; Slava Strebkov; ofw at lists.openfabrics.org
Subject: RE: [ofw] [PATCH] affinity options

 

I didn't see any response to the comments regarding the need to define the
special value of 0xFFFFFFFF.  Is there a reason why we can't just use an index
and let the user specify 0?  (I.e. Is there a reason why we need a way to get
the last cpu over the first?)

 

  _____  

From: ofw-bounces at lists.openfabrics.org
[mailto:ofw-bounces at lists.openfabrics.org] On Behalf Of Leonid Keller
Sent: Monday, April 07, 2008 4:20 AM
To: Slava Strebkov; ofw at lists.openfabrics.org
Subject: RE: [ofw] [PATCH] affinity options

 

Done in rev. 1047, thank you.

 


  _____  


From: ofw-bounces at lists.openfabrics.org
[mailto:ofw-bounces at lists.openfabrics.org] On Behalf Of Slava Strebkov
Sent: Wednesday, April 02, 2008 5:47 PM
To: ofw at lists.openfabrics.org
Subject: [ofw] [PATCH] affinity options

Hi,

The following patch provides a way to user to specify the cpu affinity mask.

Setting the value of ProcessorAffinity to FFFFFFFF binds interrupt to last cpu
on machine.

 

Index: hw/mthca/kernel/hca_pnp.c

===================================================================

--- hw/mthca/kernel/hca_pnp.c   (revision 1031)

+++ hw/mthca/kernel/hca_pnp.c (working copy)

@@ -678,6 +678,29 @@

                        if( pHcaRes->Type == CmResourceTypeInterrupt )

                        {

                                    p_ext->interruptInfo = *pHostRes;

+            if ( g_processor_affinity == 0xFFFFFFFF ) 

+                                  {

+                                              /* 

+                                              * Calculate the mask of the last
processor

+                                              */

+                                              KAFFINITY
n_active_processors_bitmask;

+                                              uint32_t
last_processor_mask = 0 , tmp_processor_mask = 1;

+                                              

+                                              n_active_processors_bitmask =
KeQueryActiveProcessors();

+                while ( tmp_processor_mask & n_active_processors_bitmask )

+                                              {

+
last_processor_mask = tmp_processor_mask;

+
tmp_processor_mask = tmp_processor_mask << 1;

+                                              }

+
p_ext->interruptInfo.u.Interrupt.Affinity = last_processor_mask; 

+                                  }

+                                  else if (g_processor_affinity != 0) 

+                                  {

+
p_ext->interruptInfo.u.Interrupt.Affinity = g_processor_affinity;


+                                  }

+                                  HCA_PRINT( TRACE_LEVEL_INFORMATION,
HCA_DBG_PNP,("Set Interrupt affinity to : 0x%08X\n",

+
(int)p_ext->interruptInfo.u.Interrupt.Affinity ));

+

                                    continue;

                        }

                        

Index: hw/mthca/kernel/mt_l2w.c

===================================================================

--- hw/mthca/kernel/mt_l2w.c      (revision 1031)

+++ hw/mthca/kernel/mt_l2w.c    (working copy)

@@ -118,7 +118,7 @@

                        (BOOLEAN)((int_info->Flags ==
CM_RESOURCE_INTERRUPT_LATCHED) ? 

                        Latched : LevelSensitive),
/* interrupt type: LATCHED or LEVEL */

                        (BOOLEAN)(int_info->ShareDisposition ==
CmResourceShareShared),    /* vector shared or not */

-                       g_processor_affinity ? g_processor_affinity :
(KAFFINITY)int_info->u.Interrupt.Affinity,       /* interrupt affinity */

+                      (KAFFINITY)int_info->u.Interrupt.Affinity,            /*
interrupt affinity */

                        FALSE
/* whether to save Float registers */

                        );

 

 

Slava Strebkov

SW Engineer

Voltaire

099718750

 

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